公开(公告)号：US5469444A

公开(公告)日：1995-11-21

申请号：US341955

申请日：1994-11-16

申请人： Tetsuo Endoh ,  Riichiro Shirota ,  Kazunori Ohuchi ,  Ryouhei Kirisawa ,  Seiichi Aritome ,  Tomoharu Tanaka ,  Yoshiyuki Tanaka

发明人： Tetsuo Endoh ,  Riichiro Shirota ,  Kazunori Ohuchi ,  Ryouhei Kirisawa ,  Seiichi Aritome ,  Tomoharu Tanaka ,  Yoshiyuki Tanaka

IPC分类号： G11C11/56 ,  G11C16/34 ,  G11C29/50 ,  G01R31/28

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/3404 ,  G11C16/3413 ,  G11C16/3418 ,  G11C16/3431 ,  G11C16/3459 ,  G11C29/50 ,  G06F2201/81 ,  G11C16/04 ,  G11C2029/0403 ,  G11C2211/5621

摘要： An EEPROM includes an array of memory cell transistors, which is divided into cell blocks each including NAND cell units of series-connected cell transistors. A sense amplifier is connected to bit lines and a comparator. A data-latch circuit is connected to the comparator, for latching a write-data supplied from a data input buffer. After desired cell transistors selected for programming in a selected block are once programmed, a write-verify operation is performed. The comparator compares the actual data read from one of the programmed cell transistors with the write-data, to verify its written state. The write-verify process checks the resulting threshold voltage for variations using first and second reference voltages defining the lower-limit and upper-limit of an allowable variation range. If the comparison results under employment of the first voltage shows that an irregularly written cell transistor remains with an insufficient threshold voltage which is so low as to fail to fall within the range, the write operation continues for the same cell transistor. If the comparison results under employment of the second voltage shows that an excess-written cell transistor remains, the block is rendered "protected" at least partially.

摘要翻译： EEPROM包括存储单元晶体管的阵列，其被分成每个包括串联连接的单元晶体管的NAND单元单元的单元块。 读出放大器连接到位线和比较器。 数据锁存电路连接到比较器，用于锁存从数据输入缓冲器提供的写入数据。 在所选择的块中选择用于编程的所需单元晶体管被一次编程之后，执行写验证操作。 比较器将从编程单元晶体管之一读取的实际数据与写入数据进行比较，以验证其写入状态。 写验证过程使用限定允许变化范围的下限和上限的第一和第二参考电压来检查所得到的阈值电压的变化。 如果使用第一电压的比较结果表明，不规则写入的单元晶体管保持不足阈值电压，其不足以落在该范围内，对于相同的单元晶体管，写操作继续进行。 如果在使用第二电压的情况下的比较结果表明剩余写入过多的单元晶体管，则该块至少部分地被“保护”。

公开(公告)号：US5379256A

公开(公告)日：1995-01-03

申请号：US223307

申请日：1994-04-05

申请人： Tomoharu Tanaka ,  Yoshiyuki Tanaka ,  Kazunori Ohuchi ,  Masaki Momodomi ,  Yoshihisa Iwata ,  Koji Sakui ,  Shinji Saito ,  Hideki Sumihara

发明人： Tomoharu Tanaka ,  Yoshiyuki Tanaka ,  Kazunori Ohuchi ,  Masaki Momodomi ,  Yoshihisa Iwata ,  Koji Sakui ,  Shinji Saito ,  Hideki Sumihara

IPC分类号： G11C7/06 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C7/00

CPC分类号： G11C16/3459 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3454 ,  G11C7/067

摘要： A plurality of electrically erasable programmable read-only memories or EEPROMs are associated with a controller LSI. Each EEPROM includes an array of floating-gate tunneling memory cell transistors arranged in rows and columns. When a sub-array of memory cell transistors providing a one-page data is selected for programming, the controller LSI performs a write/verify operation as follows the electrically written state after the programming of the selected memory cell transistors is verified by checking their threshold values for variations, and when any potentially insufficient cell transistor remains among them, the rewrite operation using a predetermined write voltage for a predetermined period of time is repeated so that the resultant write state may come closer to a satisfiable reference state. Each rewrite/verify operation is performed by applying the write voltage to the insufficient cell transistor for a predetermined period of time.

摘要翻译： 多个电可擦除可编程只读存储器或EEPROM与控制器LSI相关联。 每个EEPROM包括以行和列排列的浮栅隧穿存储单元晶体管阵列。 当选择提供单页数据的存储单元晶体管的子阵列进行编程时，控制器LSI通过检查所选存储单元晶体管的阈值来验证所选择的存储单元晶体管的编程之后，如下进行写入/校验操作 变化的值，并且当任何潜在的不足的单元晶体管保持在其中之间时，重复使用预定时间段的预定写入电压的重写操作，使得所得到的写入状态可能更接近可满足的参考状态。 通过将写入电压施加到不足的单元晶体管预定时间段来执行每个重写/验证操作。

公开(公告)号：US5361227A

公开(公告)日：1994-11-01

申请号：US992653

申请日：1992-12-18

申请人： Tomoharu Tanaka ,  Masaki Momodomi ,  Hideo Kato ,  Hiroto Nakai ,  Yoshiyuki Tanaka ,  Riichiro Shirota ,  Seiichi Aritome ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Hiroshi Nakamura ,  Hideko Odaira ,  Yutaka Okamoto ,  Masamichi Asano ,  Kaoru Tokushige

发明人： Tomoharu Tanaka ,  Masaki Momodomi ,  Hideo Kato ,  Hiroto Nakai ,  Yoshiyuki Tanaka ,  Riichiro Shirota ,  Seiichi Aritome ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Hiroshi Nakamura ,  Hideko Odaira ,  Yutaka Okamoto ,  Masamichi Asano ,  Kaoru Tokushige

IPC分类号： G06F11/10 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24 ,  G11C16/34 ,  G11C29/00 ,  G11C29/34 ,  G11C29/52 ,  G11C13/00

CPC分类号： G11C29/785 ,  G06F11/1008 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3454 ,  G11C29/34 ,  G11C29/52 ,  G06F11/1068 ,  G06F2201/81 ,  G06F2212/2022

摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

摘要翻译： 可以缩短程序验证和擦除验证操作所需的时间。 即使重复执行写入和擦除操作，也可以抑制存储单元的阈值变化。 在编程和擦除操作之后，可以根据每个位线上的电位的预充电之后的所有位线同时判断操作，而不改变列地址。 在数据重写操作中，通过改变数据寄存器中的数据，对具有一次适当写入的数据的存储单元不进行重写操作。

公开(公告)号：US5357462A

公开(公告)日：1994-10-18

申请号：US948002

申请日：1992-09-21

申请人： Tomoharu Tanaka ,  Yoshiyuki Tanaka ,  Hiroshi Nakamura ,  Hideko Odaira

发明人： Tomoharu Tanaka ,  Yoshiyuki Tanaka ,  Hiroshi Nakamura ,  Hideko Odaira

IPC分类号： G11C16/10 ,  G11C16/12 ,  G11C16/26 ,  G11C16/34 ,  G11C16/02

CPC分类号： G11C16/3459 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26 ,  G11C16/3454

摘要： A NAND-cell type EEPROM includes an array of memory cells connected to bit lines. Each cell includes one transistor with a floating gate and a control gate electrode, wherein electrons are tunneled to or from the floating gate to write a data thereinto. A sense/latch circuit is connected to the bit lines, and selectively performs a sense operation and a latch operation of the write data. A program controller is provided for writing the data into a selected memory cell in a designated area, and for reading the data written in the selected cell to verify whether or not its resultant threshold voltage falls within an allowable range. If it is insufficient, the data is rewritten thereinto. A rewrite-data setting section is provided for performing a logic operation with respect to a read data from the selected cell and the write data being latched in the sense/latch circuit, and for updating automatically a rewrite data being stored in the sense/latch circuit with respect to every bit line in accordance with the actual write state as being verified. The sense/latch circuit includes a CMOS flip-flop circuit, which acts as a data-latch at the beginning of the verify operation, and serves as a sense amplifier once after it is reset.

摘要翻译： NAND单元型EEPROM包括连接到位线的存储单元的阵列。 每个单元包括具有浮置栅极和控制栅极电极的一个晶体管，其中电子被隧道传输到浮动栅极或从浮动栅极传输到其中以写入数据。 感测/锁存电路连接到位线，并且有选择地执行写数据的检测操作和锁存操作。 提供了一种程序控制器，用于将数据写入指定区域中的所选择的存储单元中，并且用于读取写入所选单元格中的数据，以验证其合成阈值电压是否在允许范围内。 如果不足，则重写数据。 提供重写数据设置部分，用于对来自所选择的单元的读取数据进行逻辑运算，并将写入数据锁存在感测/锁存电路中，并且自动更新存储在感测/锁存器中的重写数据 根据实际写入状态对每个位线进行电路验证。 感测/锁存电路包括CMOS触发器电路，其在验证操作开始时用作数据锁存器，并且在复位之后用作读出放大器。

公开(公告)号：US5278794A

公开(公告)日：1994-01-11

申请号：US960882

申请日：1992-10-14

申请人： Yoshiyuki Tanaka ,  Yasuo Itoh ,  Masaki Momodomi ,  Yoshihisa Iwata ,  Tomoharu Tanaka

发明人： Yoshiyuki Tanaka ,  Yasuo Itoh ,  Masaki Momodomi ,  Yoshihisa Iwata ,  Tomoharu Tanaka

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  G11C11/40 ,  G11C5/02

CPC分类号： G11C29/789 ,  G11C16/0483 ,  G11C29/808 ,  G11C29/82

摘要： A NAND-cell type electrically erasable and programmable read only memory includes an array of rows and columns of memory cells associated with parallel bit lines on a semiconductive substrate. Each memory cell essentially consists of a floating-gate field effect transistor having a floating gate and an insulated control gate. The memory cell array is divided into a plurality of cell blocks, each of which includes NAND cell sections each including a predetermined number of a series-connected memory cell transistors. A redundancy cell section is provided which includes an array of redundancy memory cells containing at least one spare cell block. A row redundancy circuit is connected to a row decoder, and is responsive to an address buffer. The redundancy circuit replaces a defective block containing a defective memory cell or cells with the spare cell block.

摘要翻译： NAND单元型电可擦除和可编程只读存储器包括与半导体基板上的并行位线相关联的存储单元的行和列阵列。 每个存储单元基本上由具有浮置栅极和绝缘控制栅极的浮栅场效应晶体管组成。 存储单元阵列被分成多个单元块，每个单元块包括每个包括预定数量的串联存储单元晶体管的NAND单元部分。 提供冗余单元部分，其包括包含至少一个备用单元块的冗余存储单元的阵列。 行冗余电路连接到行解码器，并响应于地址缓冲器。 冗余电路用备用单元块替代含有缺陷存储单元或单元的缺陷块。

公开(公告)号：US5043942A

公开(公告)日：1991-08-27

申请号：US532627

申请日：1990-06-04

申请人： Yoshihisa Iwata ,  Masaki Momodomi ,  Yasuo Itoh ,  Tomoharu Tanaka ,  Hideko Odaira

发明人： Yoshihisa Iwata ,  Masaki Momodomi ,  Yasuo Itoh ,  Tomoharu Tanaka ,  Hideko Odaira

IPC分类号： G11C17/00 ,  G11C8/10 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/16 ,  H01L21/8247 ,  H01L27/112 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C8/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  H01L27/112

摘要： A NAND cell type EEPROM has a substrate, parallel bit lines formed above the substrate, and a memory cell section including an array of NAND type cell units associated with the same corresponding bit line. Each of the NAND type cell units has a series-circuit of eight data storage transistors and at least one selection transistor. Each data storage transistor has a floating gate for storing carriers injected thereinto by tunneling and a control gate respectively connected to word lines. A control gate driver circuit is provided in common for all the NAND type cell units that are assisted with the same bit line. Transfer gates are connected between the common driver circuit and the NAND cell units.

摘要翻译： NAND单元型EEPROM具有基板，形成在基板上方的并行位线以及包括与相同对应位线相关联的NAND型单元单元的阵列的存储单元部分。 每个NAND型单元单元具有八个数据存储晶体管和至少一个选择晶体管的串联电路。 每个数据存储晶体管具有用于存储通过隧道注入的载流子的浮动栅极和分别连接到字线的控制栅极。 为同一位线辅助的所有NAND型单元单元共同提供控制栅极驱动电路。 传输门连接在公共驱动电路和NAND单元之间。

公开(公告)号：US4996669A

公开(公告)日：1991-02-26

申请号：US489967

申请日：1990-03-07

申请人： Tetsuo Endoh ,  Riichiro Shirota ,  Masaki Momodomi ,  Tomoharu Tanaka ,  Fujio Masuoka ,  Shigeyoshi Watanabe

发明人： Tetsuo Endoh ,  Riichiro Shirota ,  Masaki Momodomi ,  Tomoharu Tanaka ,  Fujio Masuoka ,  Shigeyoshi Watanabe

IPC分类号： G11C16/04

CPC分类号： G11C16/0483

摘要： An electrically erasable programmable read-only memory with a NAND cell structure has parallel bit lines, and memory cells defining NAND cell blocks, each of which has a series-circuit of memory cell transistors. Each transistor has a floating gate and a control gate. Parallel word lines are connected to the control gates of the cell transistors. The first, second and third intermediate voltages are used in the data write mode: the first voltage is lower than the "H" level voltage and higher than the "L" level voltage; the second and third voltages are higher than the first voltage and lower than the "H" level voltage. Data is written into a selected memory cell transistor of a NAND cell block, by applying the "H" level voltage to a word line connected to the selected transistor, applying the second voltage to the remaining unselected word lines, applying a corresponding bit line associated with the selected transistor with one of the first and third voltages which is selected in accordance with a logic level of the data, and applying unselected bit lines with the third voltage, whereby carriers are moved by tunneling from or to the floating gate of the selected memory cell transistor.

摘要翻译： 具有NAND单元结构的电可擦除可编程只读存储器具有并行位线，以及限定NAND单元块的存储器单元，每个存储单元具有存储单元晶体管的串联电路。 每个晶体管都有一个浮动栅极和一个控制栅极。 并行字线连接到单元晶体管的控制栅极。 在数据写入模式下使用第一，第二和第三中间电压：第一电压低于“H”电平电压并高于“L”电平电压; 第二和第三电压高于第一电压并低于“H”电平电压。 将数据写入NAND单元块的选定的存储单元晶体管中，通过将“H”电平电压施加到连接到所选晶体管的字线，将第二电压施加到剩余的未选字线，施加相应的位线 其中所选择的晶体管具有根据数据的逻辑电平选择的第一和第三电压中的一个，以及施加具有第三电压的未选择的位线，由此通过隧道从所选择的浮动栅极或者所选择的浮动栅极 存储单元晶体管。

公开(公告)号：US20120163091A1

公开(公告)日：2012-06-28

申请号：US13413779

申请日：2012-03-07

申请人： Noboru Shibata ,  Tomoharu Tanaka

发明人： Noboru Shibata ,  Tomoharu Tanaka

IPC分类号： G11C16/10

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5648

摘要： A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k

摘要翻译： 存储单元阵列被配置为具有以矩阵形式布置的多个存储单元，每个存储单元连接到字线和位线，并且能够存储n个值（n是等于或大于其的自然数） 比3）。 控制电路根据输入数据控制字线和位线的电位，并将数据写入存储单元。 控制电路在写入操作中将数据写入存储单元中的k值阈值电压（k <= n），对位线进行一次预充电，然后改变字线的电位i次，以验证是否 存储器单元已达到i值（i <= k）阈值电压。

公开(公告)号：US08111551B2

公开(公告)日：2012-02-07

申请号：US13099024

申请日：2011-05-02

申请人： Tomoharu Tanaka ,  Koichi Kawai ,  Khandker N Quader

发明人： Tomoharu Tanaka ,  Koichi Kawai ,  Khandker N Quader

IPC分类号： G11C16/04 ,  G11C7/00

CPC分类号： G11C16/22

摘要： A nonvolatile semiconductor memory device includes a memory cell array constituted by a plurality of memory blocks, an interface, a write circuit, and a read circuit. A protect flag is written in the memory block. The readout protect flag can be output to an external device through the interface. When a write command is input from the interface, the write circuit executes the write command when the protect flag in the selected memory block has a first value and does not execute the write command when the protect flag has a second value.

摘要翻译： 非易失性半导体存储器件包括由多个存储块，接口，写入电路和读取电路构成的存储单元阵列。 保护标志写入存储器块。 读出保护标志可以通过接口输出到外部设备。 当从接口输入写入命令时，当所选择的存储器块中的保护标志具有第一值并且当保护标志具有第二值时，写入电路执行写入命令，并且不执行写入命令。

公开(公告)号：US20110188315A1

公开(公告)日：2011-08-04

申请号：US13079134

申请日：2011-04-04

申请人： Hiroshi Nakamura ,  Tomoharu Tanaka

发明人： Hiroshi Nakamura ,  Tomoharu Tanaka

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/30

摘要： A non-volatile semiconductor memory device includes a memory cell array of data-rewritable non-volatile memory cells or memory cell units containing the memory cells, and a plurality of word lines each commonly connected to the memory cells on the same row in the memory cell array. In write pulse applying during data writing, a high voltage for writing is applied to a selected word line, and an intermediate voltage for writing is applied to at least two of non-selected word lines. The beginning of charging a first word line located between the selected word line and a source line to a first intermediate voltage for writing is followed by the beginning of charging a second word line located between the selected word line and a bit line contact to a second intermediate voltage for writing.

摘要翻译： 非挥发性半导体存储器件包括数据可重写非易失性存储器单元的存储单元阵列或包含存储单元的存储单元单元，以及多个字线，每个字线共同连接到存储器中相同行上的存储器单元 单元格阵列。 在数据写入期间的写入脉冲施加中，写入用的高电压被施加到所选择的字线，并且用于写入的中间电压被施加到至少两个未被选择的字线。 将位于所选择的字线和源极线之间的第一字线充电到用于写入的第一中间电压的开始之后，将位于所选择的字线和位线接触之间的第二字线开始充电到第二 写入中间电压。