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    Ferroelectric/high dielectric constant integrated circuit and method of fabricating same
    81.
    发明授权
    Ferroelectric/high dielectric constant integrated circuit and method of fabricating same 失效
    铁电/高介电常数集成电路及其制造方法

    公开(公告)号：US6051858A

    公开(公告)日：2000-04-18

    申请号：US892699

    申请日：1997-07-15

    申请人： Hiroto Uchida ,  Nobuyuki Soyama ,  Katsumi Ogi ,  Michael C. Scott ,  Joseph D. Cuchiaro ,  Larry D. McMillan ,  Carlos A. Paz de Araujo

    发明人： Hiroto Uchida ,  Nobuyuki Soyama ,  Katsumi Ogi ,  Michael C. Scott ,  Joseph D. Cuchiaro ,  Larry D. McMillan ,  Carlos A. Paz de Araujo

    IPC分类号： H01L21/8247 ,  H01L21/02 ,  H01L21/316 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76

    CPC分类号： H01L27/11502 ,  H01L28/55

    摘要： A transistor on a silicon substrate is covered by an insulating layer. A conducting plug passes through the insulating layer to the transistor drain. The bottom electrode of a ferroelectric capacitor that directly overlies the plug and drain contacts the plug. The ferroelectric layer is self-patterned and completely overlies the memory cell. A self-patterned sacrificial layer completely overlies the ferroelectric layer. The bottom electrode of the capacitor is completely enclosed by the ferroelectric layer, the insulating layer, and the conducting plug. The sacrificial layer comprises either: a) a metal selected from a first metal group consisting of tantalum, hafnium, tungsten, niobium and zirconium; or b) a metallic compound comprising one or more metals selected from a second group of metals consisting of titanium, tantalum, hafnium, tungsten, niobium and zirconium compounded with one or more metals from a third group of metals consisting of strontium, calcium, barium, bismuth, cadmium, and lead, such as strontium tantalate, tantalum oxide, bismuth deficient strontium bismuth tantalate, strontium titanate, strontium zirconate, strontium niobate, tantalum nitride, and tantalum oxynitride.

    摘要翻译： 硅衬底上的晶体管被​​绝缘层覆盖。 导电插塞通过绝缘层到晶体管漏极。 直接覆盖插头和漏极的铁电电容器的底部电极接触插头。 铁电层是自我构图的，并且完全覆盖在存储单元上。 自图案牺牲层完全覆盖铁电层。 电容器的底部电极被铁电体层，绝缘层和导电插塞完全包围。 牺牲层包括：a）选自由钽，铪，钨，铌和锆组成的第一金属组的金属; 或b）金属化合物，其包含一种或多种金属，所述金属选自由钛，钽，铪，钨，铌和锆组成的第二组金属，所述金属由一种或多种金属组成，所述第三组金属由锶，钙，钡 ，铋，镉和铅，例如钽酸锶，氧化钽，铋铋铋钽酸锶，钛酸锶，锆酸锶，铌酸铌，氮化钽和氮氧化钽。

    Ferroelectric memory and non-volatile memory cell for same
    86.
    发明授权
    Ferroelectric memory and non-volatile memory cell for same 失效
    铁电存储器和非易失性存储器单元相同

    公开(公告)号：US5541870A

    公开(公告)日：1996-07-30

    申请号：US330989

    申请日：1994-10-28

    申请人： Takashi Mihara ,  Hitoshi Watanabe ,  Hiroyuki Yoshimori ,  Carlos A. Paz de Araujo ,  Larry D. McMillan

    发明人： Takashi Mihara ,  Hitoshi Watanabe ,  Hiroyuki Yoshimori ,  Carlos A. Paz de Araujo ,  Larry D. McMillan

    IPC分类号： G11C17/00 ,  G11C11/22 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/11502 ,  G11C11/22

    摘要： A non-volatile integrated circuit memory in which the memory cell includes a first transistor gate overlying a first channel region, a ferroelectric material overlying a second channel region, and a second transistor gate overlying a third channel region. The channel regions are connected in series, and preferably are contiguous portions of a single semiconducting channel. The firm channel is connected to a plate voltage that is 20% to 50% of the coercive voltage of the ferroelectric material. A sense amplifier is connected to the third channel region via a bit line. The rise of the bit line after reading a logic "1" state of the cell is prevented from disturbing the ferroelectric material by shutting off the third channel before the sense amplifier rises.

    摘要翻译： 一种非易失性集成电路存储器，其中存储单元包括覆盖第一沟道区的第一晶体管栅极，覆盖第二沟道区的铁电材料和覆盖第三沟道区的第二晶体管栅极。 通道区域串联连接，优选地是单个半导体通道的连续部分。 固体通道连接到铁电体的矫顽电压的20％至50％的板电压。 读出放大器通过位线连接到第三通道区域。 读出逻辑“1”状态之后的位线的上升通过在读出放大器上升之前切断第三通道来防止铁电材料的干扰。