公开(公告)号：US20080171418A1

公开(公告)日：2008-07-17

申请号：US12054545

申请日：2008-03-25

申请人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Cart J. Radens ,  Li-Kong Wang ,  Kwong Hon Wong

发明人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Cart J. Radens ,  Li-Kong Wang ,  Kwong Hon Wong

IPC分类号： H01L21/02

CPC分类号： H01C7/005 ,  H01C7/006 ,  H01C17/075 ,  H01G4/18 ,  H01G4/33 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/5328 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for an integrated circuit chip has a logic core which includes a plurality of insulating and conducting levels, an exterior conductor level and passive devices having a conductive polymer directly connected to the exterior conductor level. The passive devices contain RF devices which also includes resistor, capacitor, and/or inductor. The resistors can be serpentine resistors and the capacitors can be interdigitated capacitors.

摘要翻译： 集成电路芯片的方法和结构具有包括多个绝缘和导电水平的逻辑芯，外部导体水平和具有直接连接到外部导体水平的导电聚合物的无源器件。 无源器件包含还包括电阻器，电容器和/或电感器的RF器件。 电阻器可以是蛇形电阻器，电容器可以是交错电容器。

公开(公告)号：US07397260B2

公开(公告)日：2008-07-08

申请号：US11163948

申请日：2005-11-04

申请人： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Ronald G. Filippi ,  Jason P. Gill ,  Tom C. Lee ,  Baozhen Li ,  Paul S. McLaughlin ,  Du B. Nguyen ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Chih-Chao Yang

发明人： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Ronald G. Filippi ,  Jason P. Gill ,  Tom C. Lee ,  Baozhen Li ,  Paul S. McLaughlin ,  Du B. Nguyen ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Chih-Chao Yang

IPC分类号： G01R31/02 ,  H01L23/58 ,  G01N25/20

CPC分类号： G01R31/2858 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (μm).

摘要翻译： 提供了诸如芯片或微电子布线基板的微电子元件，其包括用于改善耐热应力的多个导电互连。 至少一些导电互连件包括金属板，金属连接线和上金属通孔。 所述金属连接线具有与所述金属板的上表面至少基本平齐的上表面，在所述周边边缘中的一个处连接到所述金属板的内端和从所述一个周边边缘水平移位的外端。 金属连接线的宽度远小于金属板的一个周边边缘的宽度，并且其长度大于一个周边边缘的宽度。 上金属通孔在与一个外围边缘水平位移至少约3微米（mum）的位置处具有与金属连接线接触的底端。

公开(公告)号：US07223691B2

公开(公告)日：2007-05-29

申请号：US10965031

申请日：2004-10-14

申请人： Cyril Cabral, Jr. ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  Patrick W. DeHaven ,  Chester T. Dziobkowski ,  Sunfei Fang ,  Terry A. Spooner ,  Tsong-Lin L. Tai ,  Kwong Hon Wong ,  Chin-Chao Yang

发明人： Cyril Cabral, Jr. ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  Patrick W. DeHaven ,  Chester T. Dziobkowski ,  Sunfei Fang ,  Terry A. Spooner ,  Tsong-Lin L. Tai ,  Kwong Hon Wong ,  Chin-Chao Yang

IPC分类号： H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76888

摘要： A novel interlevel contact via structure having low contact resistance and improved reliability, and method of forming the contact via. The method comprises steps of: etching an opening through an interlevel dielectric layer to expose an underlying metal (Copper) layer surface; and, performing a low energy ion implant of an inert gas (Nitrogen) into the exposed metal underneath; and, depositing a refractory liner into the walls and bottom via structure which will have a lower contact resistance due to the presence of the proceeding inert gas implantation. Preferably, the inert Nitrogen gas reacts with the underlying exposed Copper metal to form a thin layer of CuN.

摘要翻译： 具有低接触电阻和改进的可靠性的新颖的层间接触通孔结构以及形成接触通孔的方法。 该方法包括以下步骤：通过层间电介质层蚀刻开口以暴露下面的金属（铜）层表面; 并且将惰性气体（氮气）的低能量离子注入进入下面暴露的金属; 并且将耐火衬垫沉积到壁和底部通孔结构中，由于进行的惰性气体注入的存在而将具有较低的接触电阻。 优选地，惰性氮气与下面暴露的铜金属反应形成一层薄的CuN。

公开(公告)号：US07115921B2

公开(公告)日：2006-10-03

申请号：US10930989

申请日：2004-08-31

申请人： Lawrence A. Clevenger ,  Timothy Joseph Dalton ,  Louis L. Hsu ,  Carl Radens ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

发明人： Lawrence A. Clevenger ,  Timothy Joseph Dalton ,  Louis L. Hsu ,  Carl Radens ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L29/80 ,  H01L29/76 ,  H01L21/337 ,  H01L21/336

CPC分类号： H01L21/28114 ,  H01L21/76895 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/66545

摘要： Gate conductors on an integrated circuit are formed with enlarged upper portions which are utilized to electrically connect the gate conductors with other devices. A semiconductor device comprises a gate conductor with an enlarged upper portion which electrically connects the gate conductor to a local diffusion region. Another semiconductor device comprises two gate conductors with enlarged upper portions which merge to create electrically interconnected gate conductors. Methods for forming the above semiconductor devices are also described and claimed.

摘要翻译： 集成电路上的栅极导体形成有用于将栅极导体与其它器件电连接的较大的上部。 半导体器件包括具有扩大上部的栅极导体，该栅极导体将栅极导体电连接到局部扩散区。 另一个半导体器件包括两个栅极导体，其具有扩大的上部，其合并以产生电互连的栅极导体。 还描述和要求保护形成上述半导体器件的方法。

公开(公告)号：US07088074B2

公开(公告)日：2006-08-08

申请号：US10039541

申请日：2002-01-02

申请人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Carl J. Radens ,  Li-Kong Wang ,  Kwong Hon Wong

发明人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Carl J. Radens ,  Li-Kong Wang ,  Kwong Hon Wong

IPC分类号： H02J7/00

CPC分类号： H01M10/425 ,  H01L23/58 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15153 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/30107 ,  H01M2/1066 ,  H01M2/204 ,  H01L2924/00014 ,  H01L2924/00

摘要： A system level device for battery and integrated circuit chip integration comprises at least one battery; at least one integrated circuit chip powered by the at least one battery; and a package connected to any of the at least one battery and the at least one integrated circuit chip, wherein the at least one battery connects to a pair of opposed upright ends of the package, wherein the at least one integrated circuit chip is disposed between the at least one battery and the package, and wherein the at least one integrated circuit chip lays on top of a portion of the package.

摘要翻译： 用于电池和集成电路芯片集成的系统级装置包括至少一个电池; 由所述至少一个电池供电的至少一个集成电路芯片; 以及连接到所述至少一个电池和所述至少一个集成电路芯片中的任一个的封装，其中所述至少一个电池连接到所述封装的一对相对的直立端，其中所述至少一个集成电路芯片设置在 所述至少一个电池和所述封装，并且其中所述至少一个集成电路芯片放置在所述封装的一部分的顶部上。

公开(公告)号：US07001835B2

公开(公告)日：2006-02-21

申请号：US10707119

申请日：2003-11-21

申请人： Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Kaushik A. Kumar ,  Stephen M. Rossnagel ,  Andrew H. Simon ,  Douglas C. La Tulipe, Jr.

发明人： Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Kaushik A. Kumar ,  Stephen M. Rossnagel ,  Andrew H. Simon ,  Douglas C. La Tulipe, Jr.

IPC分类号： H01L21/4763

CPC分类号： H01L23/544 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/2855 ,  H01L21/76841 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A hardmask layer in the back end of an integrated circuit is formed from TaN having a composition of less than 50% Ta and a resistivity greater than 400 μOhm-cm, so that it is substantially transparent in the visible and permits visual alignment of upper and lower alignment marks through the hardmask and intervening layer(s) of ILD. A preferred method of formation of the hardmask is by sputter deposition of Ta in an ambient containing N2 and a flow rate such that (N2 flow)/(N2+carrier flow)>0.5.

摘要翻译： 集成电路后端的硬掩模层由具有小于50％Ta且电阻率大于400μΩ-cm的组成的TaN形成，使得其在可见光中基本上是透明的并且允许上和 通过硬掩模和ILD的中间层降低对准标记。 形成硬掩模的优选方法是通过在含有N 2 O 2的环境中溅射沉积Ta并使流速使得（N 2 N 2 O 2）/（N _{2 +载体流）> 0.5。}

公开(公告)号：US06909145B2

公开(公告)日：2005-06-21

申请号：US10252661

申请日：2002-09-23

申请人： Cyril Cabral, Jr. ,  Lawrence A. Clevenger ,  Louis L. Hsu ,  Joseph F. Shepard, Jr. ,  Kwong Hon Wong

发明人： Cyril Cabral, Jr. ,  Lawrence A. Clevenger ,  Louis L. Hsu ,  Joseph F. Shepard, Jr. ,  Kwong Hon Wong

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/6653 ,  H01L21/28061 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/6659

摘要： A method and structure for a metal oxide semiconductor transistor having a substrate, a well region in the substrate, source and drain regions on opposite sides of the well region in the substrate, a gate insulator over the well region of the substrate, a polysilicon gate conductor over the gate insulator, and metallic spacers on sides of the gate conductor.

摘要翻译： 一种金属氧化物半导体晶体管的方法和结构，其具有衬底，衬底中的阱区，衬底中的阱区的相对侧上的源极和漏极区，衬底的阱区上的栅极绝缘体，多晶硅栅极 栅极绝缘体上的导体，以及栅极导体侧面的金属间隔物。

公开(公告)号：US06768063B2

公开(公告)日：2004-07-27

申请号：US09943827

申请日：2001-08-31

申请人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Carl J. Radens ,  Li-Kong Wang ,  Kwong Hon Wong

发明人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Carl J. Radens ,  Li-Kong Wang ,  Kwong Hon Wong

IPC分类号： H05K111

CPC分类号： H05K3/24 ,  G01N27/226 ,  H01L23/4824 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for an electrode device, whereby a second electrode is deposited on a first electrode such that there is an increase in the capacitive coupling between the pair of conductive electrodes. The electrodes are self-aligning such that the patterning manufacturing process is insensitive to variations in the positional placement of the pattern on the substrate. Moreover, a single lithographic masking layer is used for forming the pair of electrodes, which are electrically isolated. Finally, the first electrode is offset from the second electrode by a chemical surface modification of the first electrode, and an anisotropic deposition of the second electrode which is shadowed by the first electrode.

摘要翻译： 一种电极装置的方法和结构，由此第二电极沉积在第一电极上，使得一对导电电极之间的电容耦合增加。 电极是自对准的，使得图案化制造工艺对图案在衬底上的位置放置的变化不敏感。 此外，单个光刻掩模层用于形成电隔离的一对电极。 最后，第一电极通过第一电极的化学表面改性和由第一电极遮蔽的第二电极的各向异性沉积而偏离第二电极。

公开(公告)号：US06743670B2

公开(公告)日：2004-06-01

申请号：US10382894

申请日：2003-03-06

申请人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Carl J Radens ,  Joseph F. Shepard, Jr.

发明人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Carl J Radens ,  Joseph F. Shepard, Jr.

IPC分类号： H01L218242

CPC分类号： H01L29/945 ,  H01L21/28194 ,  H01L21/31604 ,  H01L21/3162 ,  H01L27/10829 ,  H01L27/1087 ,  H01L29/517 ,  H01L29/66181

摘要： A method and structure for an improved DRAM (dynamic random access memory) dielectric structure, whereby a new high-k material is implemented for both the support devices used as the gate dielectric as well as the capacitor dielectric. The method forms both deep isolated trench regions used for capacitor devices, and shallow isolated trench regions for support devices. The method also forms two different insulator layers, where one insulator layer with a uniform high-k dielectric constant is used for the deep trench regions and the support regions. The other insulator layer is used in the array regions in between the shallow trench regions.

摘要翻译： 用于改进的DRAM（动态随机存取存储器）电介质结构的方法和结构，由此为用作栅极电介质的支撑器件以及电容器电介质实现新的高k材料。 该方法形成用于电容器器件的深的隔离沟槽区域和用于支持器件的浅隔离沟槽区域。 该方法还形成两个不同的绝缘体层，其中具有均匀的高k介电常数的一个绝缘体层用于深沟槽区域和支撑区域。 另一个绝缘体层用于浅沟槽区域之间的阵列区域。

公开(公告)号：US06696759B2

公开(公告)日：2004-02-24

申请号：US10021123

申请日：2001-10-30

申请人： Lawrence A. Clevenger ,  Louis L. C. Hsu ,  Jeremy K. Stephens ,  Michael Wise

发明人： Lawrence A. Clevenger ,  Louis L. C. Hsu ,  Jeremy K. Stephens ,  Michael Wise

IPC分类号： H01L2348

CPC分类号： H01L21/31053 ,  H01L21/28525 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/7684

摘要： A semiconductor structure includes a diamond-like carbon layer as a polish-stop for patterning a metal level into an inter-level dielectric substrate in a damascene process flow. The semiconductor structure includes a substrate having a dielectric layer followed by the diamond-like carbon layer on a surface thereof. The diamond-like carbon layer is used as a hard-mask for forming conductive metal features from grown substrate material that fills a plurality of openings in the substrate, therein forming a semiconductor island structure, The semiconductor structure has a planar surface at the diamond-like carbon layer and the grown substrate material, whereby the diamond-like carbon polish-stop layer allows for over-planarization of the semiconductor island structure to provide an improved planar surface having a sufficient decrease in topography.

摘要翻译： 半导体结构包括金刚石状碳层，作为用于在金属镶嵌工艺流程中将金属水平图案化成层间电介质基板的抛光止动件。 该半导体结构包括其表面上具有介电层，然后是类金刚石碳层的基板。 金刚石状碳层用作用于形成导电金属特征的硬掩模，用于形成填充衬底中的多个开口的生长的衬底材料，其中形成半导体岛结构。半导体结构在金刚石 - 类似碳层和生长的基底材料，由此金刚石状碳抛光 - 停止层允许半导体岛结构的过平坦化，以提供具有足够的形貌降低的改进的平面表面。