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    Methods of fabricating integrated structures, and methods of forming vertically-stacked memory cells
    82.
    发明授权
    Methods of fabricating integrated structures, and methods of forming vertically-stacked memory cells 有权
    制造集成结构的方法，以及形成垂直堆叠的存储单元的方法

    公开(公告)号：US09305938B2

    公开(公告)日：2016-04-05

    申请号：US14824942

    申请日：2015-08-12

    Applicant: Micron Technology, Inc.

    Inventor： Fatma Arzum Simsek-Ege ,  Aaron R. Wilson

    IPC: H01L27/115 ,  H01L27/108

    CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/10844 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/4966

    Abstract: Some embodiments include a method of fabricating integrated structures. A metal-containing material is formed over a stack of alternating first and second levels. An opening is formed through the metal-containing material and the stack. Repeating vertically-stacked electrical components are formed along the stack at sidewalls of the opening. Some embodiments include a method of forming vertically-stacked memory cells. Metal-containing material is formed over a stack of alternating silicon dioxide levels and conductively-doped silicon levels. A first opening is formed through the metal-containing material and the stack. Cavities are formed to extend into the conductively-doped silicon levels along sidewalls of the first opening. Charge-blocking dielectric and charge-storage structures are formed within the cavities to leave a second opening. Sidewalls of the second opening are lined with gate dielectric and then channel material is formed within the second opening.

    Abstract translation: 一些实施例包括制造集成结构的方法。 在交替的第一和第二水平的叠层上形成含金属的材料。 通过含金属材料和叠层形成开口。 在开口的侧壁处沿着堆叠形成重叠的垂直堆叠的电部件。 一些实施例包括形成垂直堆叠的存储单元的方法。 含金属的材料形成在交替的二氧化硅水平和导电掺杂的硅层上。 通过含金属材料和叠层形成第一开口。 腔体形成为延伸到沿着第一开口的侧壁的导电掺杂的硅层中。 电荷阻挡电介质和电荷存储结构形成在空腔内以留下第二开口。 第二开口的侧壁衬有栅极电介质，然后在第二开口内形成通道材料。

    Memory including blocking dielectric in etch stop tier
    84.
    发明授权
    Memory including blocking dielectric in etch stop tier 有权
    存储器包括蚀刻停止层中的阻挡电介质

    公开(公告)号：US09064970B2

    公开(公告)日：2015-06-23

    申请号：US13864794

    申请日：2013-04-17

    Applicant: Micron Technology, Inc.

    Inventor： Fatma Arzum Simsek-Ege ,  John Hopkins ,  Srikant Jayanti

    IPC: H01L27/115 ,  H01L29/792 ,  H01L29/66

    CPC classification number: H01L27/11556 ,  H01L27/11524 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

    Abstract: Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to a source, an etch stop tier over the source, and a stack of alternating dielectric tiers and conductive tiers over the etch stop tier. The etch stop tier can comprise a blocking dielectric adjacent to the pillar. In another embodiment, the etch stop tier can comprise a blocking dielectric adjacent to the pillar, and a plurality of dielectric films horizontally extending from the blocking dielectric into the etch stop tier.

    Abstract translation: 垂直记忆及其制备方法一般在此讨论。 在一个实施例中，垂直存储器可以包括延伸到源的垂直柱，源极上的蚀刻停止层，以及蚀刻停止层上方的交替介电层和导电层的堆叠。 蚀刻停止层可以包括邻近柱的阻挡电介质。 在另一个实施例中，蚀刻停止层可以包括邻近柱的阻挡电介质和从阻挡电介质水平延伸到蚀刻停止层中的多个电介质膜。

    SINGLE-CRYSTAL TRANSISTORS FOR MEMORY DEVICES
    87.
    发明申请
    SINGLE-CRYSTAL TRANSISTORS FOR MEMORY DEVICES 有权

    公开(公告)号：US20250142909A1

    公开(公告)日：2025-05-01

    申请号：US19008075

    申请日：2025-01-02

    Applicant: Micron Technology, Inc.

    Inventor： Fatma Arzum Simsek-Ege ,  Masihhur R. Laskar ,  Nicholas R. Tapias ,  Darwin Franseda Fan ,  Manuj Nahar

    IPC: H10D62/40 ,  H10B12/00 ,  H10B53/30 ,  H10D62/17

    Abstract: Methods, systems, and devices for single-crystal transistors for memory devices are described. In some examples, a cavity may be formed through at least a portion of one or more dielectric materials, which may be deposited above a deck of memory cells. The cavity may include a taper, such as a taper toward a point, or a taper having an included angle that is within a range, or a taper from a cross-sectional area to some fraction of the cross-sectional area, among other examples. A semiconductor material may be deposited in the cavity and above the one or more dielectric materials, and formed in a single crystalline arrangement based on heating and cooling the deposited semiconductor material. One or more portions of a transistor, such as a channel portion of a transistor, may be formed at least in part by doping the single crystalline arrangement of the semiconductor material.

    STRUCTURES FOR WORD LINE MULTIPLEXING IN THREE-DIMENSIONAL MEMORY ARRAYS
    88.
    发明申请
    STRUCTURES FOR WORD LINE MULTIPLEXING IN THREE-DIMENSIONAL MEMORY ARRAYS 有权

    公开(公告)号：US20250118341A1

    公开(公告)日：2025-04-10

    申请号：US18919142

    申请日：2024-10-17

    Applicant: Micron Technology, Inc.

    Inventor： Fatma Arzum Simsek-Ege ,  Mingdong Cui ,  Richard E. Fackenthal

    IPC: G11C5/02 ,  G11C5/06 ,  G11C8/14 ,  H10B12/00

    Abstract: Methods, systems, and devices for structures for word line multiplexing in three-dimensional memory arrays are described. A memory die may include circuitry for access line multiplexing in regions adjacent to or between staircase regions. For example, a multiplexing region may include, for each word line of a stack of word lines, a respective first portion of a semiconductor material and a respective second portion of the semiconductor material, and may also include one or more gate material portions operable to modulate a conductivity between respective first and second portions. Each word line may be coupled with the respective first portion of the semiconductor material, such that biasing of the gate material portions may couple the word lines with the respective second portion of the semiconductor material. Such features may support various techniques for multiplexing associated with the stack of word lines, or among multiple stacks of word lines, or both.

    Single-crystal transistors for memory devices
    89.
    发明授权
    Single-crystal transistors for memory devices 有权

    公开(公告)号：US12224310B2

    公开(公告)日：2025-02-11

    申请号：US18531525

    申请日：2023-12-06

    Applicant: Micron Technology, Inc.

    Inventor： Fatma Arzum Simsek-Ege ,  Masihhur R. Laskar ,  Nicholas R. Tapias ,  Darwin Franseda Fan ,  Manuj Nahar

    IPC: H01L29/10 ,  H01L29/04 ,  H10B12/00 ,  H10B53/30

    Abstract: Methods, systems, and devices for single-crystal transistors for memory devices are described. In some examples, a cavity may be formed through at least a portion of one or more dielectric materials, which may be deposited above a deck of memory cells. The cavity may include a taper, such as a taper toward a point, or a taper having an included angle that is within a range, or a taper from a cross-sectional area to some fraction of the cross-sectional area, among other examples. A semiconductor material may be deposited in the cavity and above the one or more dielectric materials, and formed in a single crystalline arrangement based on heating and cooling the deposited semiconductor material. One or more portions of a transistor, such as a channel portion of a transistor, may be formed at least in part by doping the single crystalline arrangement of the semiconductor material.

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