公开(公告)号：US08409925B2

公开(公告)日：2013-04-02

申请号：US13178375

申请日：2011-07-07

申请人： Hung-Jen Lee ,  Shu-Ming Chang ,  Chen-Han Chiang ,  Tsang-Yu Liu ,  Yen-Shih Ho

发明人： Hung-Jen Lee ,  Shu-Ming Chang ,  Chen-Han Chiang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC分类号： H01L21/00

CPC分类号： H01L23/544 ,  H01L21/561 ,  H01L21/6836 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/13 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2223/5446 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/131 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/29124 ,  H01L2224/2957 ,  H01L2224/296 ,  H01L2224/3003 ,  H01L2224/30155 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/83125 ,  H01L2224/83127 ,  H01L2224/83192 ,  H01L2224/83895 ,  H01L2224/94 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1461 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2924/00

摘要： An embodiment of the present invention provides a manufacturing method of a chip package structure including: providing a first substrate having a plurality of predetermined scribe lines defined thereon, wherein the predetermined scribe lines define a plurality of device regions; bonding a second substrate to the first substrate, wherein a spacing layer is disposed therebetween and has a plurality of chip support rings located in the device regions respectively and a cutting support structure located on peripheries of the chip support rings, and the spacing layer has a gap pattern separating the cutting support structure from the chip support rings; and cutting the first substrate and the second substrate to form a plurality of chip packages. Another embodiment of the present invention provides a chip package structure.

公开(公告)号：US08367477B2

公开(公告)日：2013-02-05

申请号：US12722486

申请日：2010-03-11

申请人： Wen-Cheng Chien ,  Ching-Yu Ni ,  Shu-Ming Chang

发明人： Wen-Cheng Chien ,  Ching-Yu Ni ,  Shu-Ming Chang

IPC分类号： H01L23/48

CPC分类号： B05D1/36 ,  B81B2207/096 ,  B81C1/00301 ,  H01L21/56 ,  H01L21/6835 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L27/14618 ,  H01L31/02002 ,  H01L31/0203 ,  H01L33/486 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01078 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/00

摘要： An embodiment of the invention provides a method for forming an electronic device package, which includes providing a carrier substrate having an upper surface and an opposite lower surface; forming a cavity from the upper surface of the carrier substrate; disposing an electronic device having a conducting electrode in the cavity; forming a filling layer in the cavity, wherein the filling layer surround the electronic device; thinning the carrier substrate from the lower surface to a predetermined thickness; forming at least a through-hole in the electronic device or the in the carrier substrate; and forming a conducting layer over a sidewall of the through-hole, wherein the conducting layer electrically connects to the conducting electrode.

公开(公告)号：US08310050B2

公开(公告)日：2012-11-13

申请号：US13024902

申请日：2011-02-10

申请人： Wei-Ming Chen ,  Shu-Ming Chang

发明人： Wei-Ming Chen ,  Shu-Ming Chang

IPC分类号： H01L23/48

CPC分类号： H01L23/49811 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/82 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/24246 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/82 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/83

摘要： A chip package is disclosed. The package includes a carrier substrate, at least two semiconductor chips, a fill material layer, a protective layer, and a plurality of conductive bumps. The carrier substrate includes a grounding region. The semiconductor chips are disposed overlying the grounding region of the carrier substrate. Each semiconductor chip includes at least one signal pad and includes at least one grounding pad electrically connected to the grounding region. The fill material layer is formed overlying the carrier substrate and covers the semiconductor chips. The protective layer covers the fill material layer. The plurality of conductive bumps is disposed overlying the protective layer and is electrically connected to the semiconductor chips. A fabrication method of the chip package is also disclosed.

摘要翻译： 公开了一种芯片封装。 封装包括载体衬底，至少两个半导体芯片，填充材料层，保护层和多个导电凸块。 载体基板包括接地区域。 半导体芯片设置在载体基板的接地区域上。 每个半导体芯片包括至少一个信号焊盘，并且包括电连接到接地区域的至少一个接地焊盘。 填充材料层形成在载体衬底上并覆盖半导体芯片。 保护层覆盖填充层。 多个导电凸块设置在保护层的上方并与半导体芯片电连接。 还公开了芯片封装的制造方法。

公开(公告)号：US08193632B2

公开(公告)日：2012-06-05

申请号：US12500780

申请日：2009-07-10

申请人： Hsiang-Hung Chang ,  Shu-Ming Chang ,  Tzu-Ying Kuo ,  Yuan-Chang Lee

发明人： Hsiang-Hung Chang ,  Shu-Ming Chang ,  Tzu-Ying Kuo ,  Yuan-Chang Lee

IPC分类号： H01L23/04

CPC分类号： H01L21/76898 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L27/14618 ,  H01L27/14643 ,  H01L27/14683 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/12105 ,  H01L2224/24226 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/00

摘要： The three-dimensional conducting structure comprises a substrate, a first redistributed conductor, a second redistributed conductor and an insulator. The substrate has an active surface, a passive surface opposite to the active one, a pad on the active surface and a through hole. The first redistributed conductor comprises a projecting portion and a receiving portion. The projecting portion is projected from the active surface and electrically connected to the pad. The receiving portion is outside the active surface and in contact with the projecting portion, both of which constitute a recess communicating with the through hole. The second redistributed conductor is positioned within the through hole and the recess, in contact with the receiving portion, and extended toward the passive surface along the through hole. The insulator is filled between the second redistributed conductor and the substrate and between the second redistributed conductor and the projecting portion.

摘要翻译： 三维导电结构包括衬底，第一再分布导体，第二再分布导体和绝缘体。 衬底具有活性表面，与活性表面相对的无源表面，活性表面上的焊盘和通孔。 第一再分布导体包括突出部分和接收部分。 突出部分从有源表面突出并电连接到焊盘。 接收部分在活性表面之外并且与突出部分接触，两者都构成与通孔连通的凹部。 第二再分布导体定位在通孔内，凹部与接收部分接触，并沿着通孔向被动表面延伸。 绝缘体填充在第二再分布导体和衬底之间以及第二再分布导体和突出部分之间。

公开(公告)号：US20110291228A1

公开(公告)日：2011-12-01

申请号：US13117151

申请日：2011-05-27

申请人： Chien-Hung Liu ,  Shu-Ming Chang

发明人： Chien-Hung Liu ,  Shu-Ming Chang

IPC分类号： H01L29/02 ,  H01L21/78

CPC分类号： H01L21/6835 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2224/11

摘要： A package structure which includes a non-conductive substrate, a conductive element, a passivation, a jointed side, a conductive layer, a solder and a solder mask is disclosed. The conductive element is disposed on a surface of the non-conductive substrate and consists of a passive element and a corresponding circuit. The passivation completely covers the conductive element and the non-conductive substrate so that the conductive element is sandwiched between the passivation and the non-conductive substrate. The conductive layer covers the jointed side which exposes part of the corresponding circuit, extends beyond the jointed side and is electrically connected to the corresponding circuit. The solder mask which completely covers the jointed side and the conductive layer selectively exposes the solder which is disposed outside the jointed side and electrically connected to the conductive layer.

摘要翻译： 公开了一种包括非导电衬底，导电元件，钝化层，接合侧，导电层，焊料和焊料掩模的封装结构。 导电元件设置在非导电衬底的表面上，由无源元件和相应的电路构成。 钝化完全覆盖导电元件和非导电衬底，使得导电元件夹在钝化层和非导电衬底之间。 导电层覆盖接合侧，露出相应电路的一部分，延伸超过接合侧并与相应的电路电连接。 完全覆盖接合侧的焊料掩模和导电层选择性地暴露设置在接合侧外侧并与导电层电连接的焊料。

公开(公告)号：US20110140267A1

公开(公告)日：2011-06-16

申请号：US12849089

申请日：2010-08-03

申请人： Chia-Lun TSAI ,  Ching-Yu Ni ,  Tien-Hao Huang ,  Chia-Ming Cheng ,  Wen-Cheng Chien ,  Nan-Chun Lin ,  Wei-Ming Chen ,  Shu-Ming Chang ,  Bai-Yao Lou

发明人： Chia-Lun TSAI ,  Ching-Yu Ni ,  Tien-Hao Huang ,  Chia-Ming Cheng ,  Wen-Cheng Chien ,  Nan-Chun Lin ,  Wei-Ming Chen ,  Shu-Ming Chang ,  Bai-Yao Lou

IPC分类号： H01L23/498 ,  H01L21/60

CPC分类号： H01L24/20 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/19 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83132 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01021 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15184 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

摘要： The invention provides an electronic device package and a method for fabricating the same. The electronic device package includes a carrier wafer. An electronic device chip with a plurality of conductive pads thereon is disposed over the carrier wafer. An isolation laminating layer includes a lower first isolation layer, which covers the carrier wafer and the electronic device chip, and an upper second isolation layer. The isolation laminating layer has a plurality of openings to expose the conductive pads. A plurality of redistribution patterns is conformably formed on the isolation laminating layer and in the openings. The redistribution patterns are electrically connected to the conductive pads, respectively. A plurality of conductive bumps is respectively formed on the redistribution patterns, electrically connected to the conductive pads.

摘要翻译： 本发明提供一种电子器件封装及其制造方法。 电子器件封装包括载体晶片。 具有多个导电焊盘的电子器件芯片设置在载体晶片上。 隔离层压层包括覆盖载体晶片和电子器件芯片的下部第一隔离层和上部第二隔离层。 隔离层压层具有多个开口以露出导电垫。 在隔离层压层和开口中顺应地形成多个再分配图案。 再分布图案分别电连接到导电焊盘。 多个导电凸块分别形成在再分布图案上，电连接到导电焊盘。

公开(公告)号：US20110127670A1

公开(公告)日：2011-06-02

申请号：US12957159

申请日：2010-11-30

申请人： Baw-Ching PERNG ,  Ying-Nan Wen ,  Shu-Ming Chang

发明人： Baw-Ching PERNG ,  Ying-Nan Wen ,  Shu-Ming Chang

IPC分类号： H01L23/48 ,  H01L21/50

CPC分类号： H01L25/50 ,  B81B2207/012 ,  B81B2207/07 ,  B81B2207/098 ,  B81C1/0023 ,  B81C2203/0109 ,  B81C2203/0792 ,  H01L21/6835 ,  H01L24/94 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/16235 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A chip package includes a substrate having an upper and a lower surface and including: at least a first contact pad; a non-optical sensor chip disposed overlying the upper surface, wherein the non-optical sensor chip includes at least a second contact pad and has a first length; a protective cap disposed overlying the non-optical sensor chip, wherein the protective cap has a second length, an extending direction of the second length is substantially parallel to that of the first length, and the second length is shorter than the first length; an IC chip disposed overlying the protective cap, wherein the IC chip includes at least a third contact pad and has a third length, and an extending direction of the third length is substantially parallel to that of the first length; and bonding wires forming electrical connections between the substrate, the non-optical sensor chip, and the IC chip.

摘要翻译： 芯片封装包括具有上表面和下表面的衬底，并且包括：至少第一接触焊盘; 设置在上表面上的非光学传感器芯片，其中所述非光学传感器芯片至少包括第二接触焊盘并具有第一长度; 设置在所述非光学传感器芯片上的保护盖，其中所述保护盖具有第二长度，所述第二长度的延伸方向基本上平行于所述第一长度的延伸方向，并且所述第二长度短于所述第一长度; 设置在所述保护盖上的IC芯片，其中所述IC芯片包括至少第三接触焊盘并具有第三长度，并且所述第三长度的延伸方向基本上与所述第一长度的延伸方向平行; 以及在基板，非光学传感器芯片和IC芯片之间形成电连接的接合线。

公开(公告)号：US07902674B2

公开(公告)日：2011-03-08

申请号：US12155715

申请日：2008-06-09

申请人： Hsiang-Hung Chang ,  Shu-Ming Chang

发明人： Hsiang-Hung Chang ,  Shu-Ming Chang

IPC分类号： H01L21/31

CPC分类号： H01L21/76898 ,  H01L21/6835 ,  H01L24/24 ,  H01L24/27 ,  H01L24/29 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2221/68377 ,  H01L2224/02372 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/056 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/24145 ,  H01L2224/274 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/32188 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05099

摘要： This invention provides a substrate having at least one bottom electrode formed therein. A plurality of dice each having at least one opening formed therein are vertically stacked together one by one by a polymer insulating layer acting as an adhering layer between them, along with the openings thereof aligned to each other to form a through hole passing through said dice. The stacked dice are joined to a bottom of the substrate with the polymer insulating layer acting as an adhering layer, making the bottom electrode of the substrate contact the through hole. An electroplating process is performed with the bottom electrode serving as an electroplating electrode to form a conductive contact passing through the dice.

摘要翻译： 本发明提供一种其中形成有至少一个底部电极的基板。 每个具有形成在其中的至少一个开口的多个骰子通过在其间作为粘合层的聚合物绝缘层一个接一个地垂直堆叠在一起，并且其开口彼此对准以形成穿过所述骰子的通孔 。 堆叠的骰子连接到基底的底部，聚合物绝缘层用作粘合层，使得基底的底部电极与通孔接触。 执行电镀工艺，其中底部电极用作电镀电极，以形成通过芯片的导电接触。

公开(公告)号：US20100163090A1

公开(公告)日：2010-07-01

申请号：US12640013

申请日：2009-12-17

申请人： Chun-Kai Liu ,  Shu-Ming Chang

发明人： Chun-Kai Liu ,  Shu-Ming Chang

IPC分类号： H01L35/28 ,  H01L21/50 ,  H01L35/34

CPC分类号： H01L23/38 ,  H01L23/3675 ,  H01L23/481 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/81 ,  H01L25/0657 ,  H01L35/32 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/1411 ,  H01L2224/16105 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81801 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06589 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A thermoelectric device including a first substrate, a plurality of conductive vias, a second substrate, a thermoelectric couple module, a first insulation layer, and a second insulation layer is provided. The first substrate has a first surface and a second surface opposite to each other. The conductive vias running through the first substrate respectively connect the first and the second surface. The second substrate faces the second surface of the first substrate. The thermoelectric couple module including a plurality of thermoelectric couples connected with each other in series is disposed between the first and the second substrate and coupled to the conductive vias. The first insulation layer is disposed between the thermoelectric couple module and the first substrate. The second insulation layer is disposed between the thermoelectric couple module and the second substrate.

摘要翻译： 提供了包括第一基板，多个导电通孔，第二基板，热电偶联模块，第一绝缘层和第二绝缘层的热电装置。 第一基板具有彼此相对的第一表面和第二表面。 穿过第一衬底的导电通孔分别连接第一和第二表面。 第二基板面向第一基板的第二表面。 包括彼此串联连接的多个热电偶的热电耦合模块设置在第一和第二基板之间并耦合到导电通孔。 第一绝缘层设置在热电偶组件和第一衬底之间。 第二绝缘层设置在热电偶组件和第二衬底之间。

公开(公告)号：US07541217B1

公开(公告)日：2009-06-02

申请号：US12198072

申请日：2008-08-25

申请人： Ying-Ching Shih ,  Shu-Ming Chang

发明人： Ying-Ching Shih ,  Shu-Ming Chang

IPC分类号： H01L21/44

CPC分类号： H01L25/0657 ,  H01L24/12 ,  H01L24/16 ,  H01L24/31 ,  H01L24/90 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05023 ,  H01L2224/05568 ,  H01L2224/1131 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/16 ,  H01L2224/2518 ,  H01L2224/83194 ,  H01L2224/90 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A fabrication method of a stacked chip structure is provided. Firstly, a first conductive layer is formed on a first surface of a wafer. Afterwards, a first patterned polymer layer is formed on the first conductive layer, and a second patterned polymer layer is formed on a second surface of the wafer. Next, a second conductive layer is electroplated on the first conductive layer and is heated to form a number of solder bumps. After that, the wafers are stacked on a substrate structure. The first patterned polymer layer disposed on a first wafer of the wafers is correspondingly connected to the second patterned polymer layer on a second wafer of the wafers. The present invention is suitable for the stacked chip structure connected by the fine-pitch solder bumps. Besides, the fabrication of the present invention is relatively simplified.

摘要翻译： 提供了堆叠式芯片结构的制造方法。 首先，在晶片的第一表面上形成第一导电层。 之后，在第一导电层上形成第一图案化聚合物层，并且在晶片的第二表面上形成第二图案化聚合物层。 接下来，将第二导电层电镀在第一导电层上并被加热以形成多个焊料凸点。 之后，将晶片堆叠在基板结构上。 设置在晶片的第一晶片上的第一图案化聚合物层相应地连接到晶片的第二晶片上的第二图案化聚合物层。 本发明适用于通过细间距焊料凸块连接的堆叠芯片结构。 此外，本发明的制造相对简化。