公开(公告)号：US20110237085A1

公开(公告)日：2011-09-29

申请号：US13152865

申请日：2011-06-03

申请人： FRANCIMAR CAMPANA SCHMITT ,  Li-Qun Xia ,  Son Van Nguyen ,  Shankar Venkataraman

发明人： FRANCIMAR CAMPANA SCHMITT ,  Li-Qun Xia ,  Son Van Nguyen ,  Shankar Venkataraman

IPC分类号： H01L21/31

CPC分类号： H01L21/76835 ,  C23C16/0272 ,  C23C16/30 ,  C23C16/325 ,  C23C16/505 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/0234 ,  H01L21/02351 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/3121 ,  H01L21/3148 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/7681 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832

摘要： Methods are provided for processing a substrate for depositing an adhesion layer having a low dielectric constant between two low k dielectric layers. In one aspect, the invention provides a method for processing a substrate including depositing a barrier layer on the substrate, wherein the barrier layer comprises silicon and carbon and has a dielectric constant less than 4, depositing a dielectric initiation layer adjacent the barrier layer, and depositing a first dielectric layer adjacent the dielectric initiation layer, wherein the dielectric layer comprises silicon, oxygen, and carbon and has a dielectric constant of about 3 or less.

摘要翻译： 提供了用于处理用于沉积在两个低k电介质层之间具有低介电常数的粘合层的衬底的方法。 一方面，本发明提供了一种处理衬底的方法，包括在衬底上沉积阻挡层，其中阻挡层包括硅和碳并具有小于4的介电常数，沉积与阻挡层相邻的电介质起始层，以及 沉积与电介质起始层相邻的第一电介质层，其中介电层包括硅，氧和碳并且具有约3或更小的介电常数。

公开(公告)号：US20100096687A1

公开(公告)日：2010-04-22

申请号：US12255617

申请日：2008-10-21

申请人： Mihaela BALSEANU ,  Vladimir Zubkov ,  Li-Qun Xia ,  Atif Noori ,  Reza Arghavani ,  Derek R. Witty ,  Amir Al-Bayati

发明人： Mihaela BALSEANU ,  Vladimir Zubkov ,  Li-Qun Xia ,  Atif Noori ,  Reza Arghavani ,  Derek R. Witty ,  Amir Al-Bayati

IPC分类号： H01L29/78 ,  H01L21/3205 ,  H01L21/31

CPC分类号： H01L21/3185 ,  H01L21/28282 ,  H01L21/3105 ,  H01L21/3115 ,  H01L21/31155 ,  H01L29/42332 ,  H01L29/7881 ,  H01L29/792

摘要： A flash memory device and methods of forming a flash memory device are provided. The flash memory device includes a doped silicon nitride layer having a dopant comprising carbon, boron or oxygen. The doped silicon nitride layer generates a higher number and higher concentration of nitrogen and silicon dangling bonds in the layer and provides an increase in charge holding capacity and charge retention time of the unit cell of a non-volatile memory device.

摘要翻译： 提供闪速存储器件和形成闪存器件的方法。 闪速存储器件包括具有包含碳，硼或氧的掺杂剂的掺杂氮化硅层。 掺杂的氮化硅层在该层中产生更高数量和更高浓度的氮和硅悬挂键，并且提供了非易失性存储器件的单元电池的电荷保持容量和电荷保留时间的增加。

公开(公告)号：US20090269923A1

公开(公告)日：2009-10-29

申请号：US12109533

申请日：2008-04-25

申请人： Sang M. Lee ,  Yong-Won Lee ,  Meiyee Shek ,  Li-Qun Xia ,  Derek R. Witty

发明人： Sang M. Lee ,  Yong-Won Lee ,  Meiyee Shek ,  Li-Qun Xia ,  Derek R. Witty

IPC分类号： H01L21/321

CPC分类号： H01L21/02074 ,  H01L21/7681 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76883 ,  H01L21/76886

摘要： A method and apparatus for processing a substrate is provided. The method of processing a substrate includes providing a substrate comprising a conductive material, performing a pre-treatment process on the conductive material, flowing a silicon based compound on the conductive material to form a silicide layer, performing a post treatment process on the silicide layer, and depositing a barrier dielectric layer on the substrate.

摘要翻译： 提供了一种用于处理衬底的方法和设备。 处理衬底的方法包括提供包括导电材料的衬底，对导电材料执行预处理工艺，在导电材料上流动硅基化合物以形成硅化物层，对硅化物层进行后处理工艺 ，并在衬底上沉积阻挡介电层。

公开(公告)号：US07601651B2

公开(公告)日：2009-10-13

申请号：US11668911

申请日：2007-01-30

申请人： Mihaela Balseanu ,  Meiyee Shek ,  Li-Qun Xia ,  Hichem M'Saad

发明人： Mihaela Balseanu ,  Meiyee Shek ,  Li-Qun Xia ,  Hichem M'Saad

IPC分类号： H01L21/31

CPC分类号： H01L21/76834 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/31612 ,  H01L21/31633 ,  H01L21/76829 ,  H01L21/76831

摘要： A method of forming a layer on a substrate in a chamber, wherein the substrate has at least one formed feature across its surface, is provided. The method includes exposing the substrate to a silicon-containing precursor in the presence of a plasma to deposit a layer, treating the deposited layer with a plasma, and repeating the exposing and treating until a desired thickness of the layer is obtained. The plasma may be generated from an oxygen-containing gas.

摘要翻译： 提供了一种在室中的衬底上形成层的方法，其中衬底在其表面上具有至少一个形成的特征。 该方法包括在存在等离子体的情况下将衬底暴露于含硅前体以沉积一层，用等离子体处理沉积层，并重复曝光和处理，直到获得所需层厚。 等离子体可以由含氧气体产生。

公开(公告)号：US07566655B2

公开(公告)日：2009-07-28

申请号：US11398436

申请日：2006-04-05

申请人： Mihaela Balseanu ,  Jia Lee ,  Mei-Yee Shek ,  Amir Al-Bayati ,  Li-Qun Xia ,  Hichem M'Saad

发明人： Mihaela Balseanu ,  Jia Lee ,  Mei-Yee Shek ,  Amir Al-Bayati ,  Li-Qun Xia ,  Hichem M'Saad

IPC分类号： H01L21/44

CPC分类号： H01L29/7843 ,  C23C16/345 ,  C23C16/56 ,  H01L21/28044 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4925 ,  H01L29/66545 ,  H01L29/66583

摘要： A process flow integration scheme employs one or more techniques to control stress in a semiconductor device formed thereby. In accordance with one embodiment, cumulative stress contributed by RTP of a nitride spacer and polysilicon gate, and subsequent deposition of a high stress etch stop layer, enhance strain and improve device performance. Germanium may be deposited or implanted into the gate structure in order to facilitate stress control.

摘要翻译： 工艺流程集成方案采用一种或多种技术来控制由此形成的半导体器件中的应力。 根据一个实施例，由氮化物间隔物和多晶硅栅极的RTP贡献的累积应力以及随后沉积高应力蚀刻停止层，增强应变并提高器件性能。 可以将锗沉积或植入栅极结构中以便于应力控制。

公开(公告)号：US20090137132A1

公开(公告)日：2009-05-28

申请号：US12365669

申请日：2009-02-04

申请人： Ritwik Bhatia ,  Li-Qun Xia ,  Chad Peterson ,  Hichem M'Saad

发明人： Ritwik Bhatia ,  Li-Qun Xia ,  Chad Peterson ,  Hichem M'Saad

IPC分类号： H01L21/31

CPC分类号： H01L21/0332 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3185 ,  H01L21/76825 ,  H01L21/76829

摘要： Methods for forming silicon nitride hard masks are provided. The silicon nitride hard masks include carbon-doped silicon nitride layers and undoped silicon nitride layers. Carbon-doped silicon nitride layers that are deposited from a mixture comprising a carbon source compound, a silicon source compound, and a nitrogen source in the presence of RF power are provided. Also provided are methods of UV post-treating silicon nitride layers to provide silicon nitride hard masks. The carbon-doped silicon nitride layers and UV post-treated silicon nitride layers have desirable wet etch rates and dry etch rates for hard mask layers.

摘要翻译： 提供了形成氮化硅硬掩模的方法。 氮化硅硬掩模包括碳掺杂的氮化硅层和未掺杂的氮化硅层。 提供了在RF功率存在下由包含碳源化合物，硅源化合物和氮源的混合物沉积的碳掺杂氮化硅层。 还提供了UV后处理氮化硅层以提供氮化硅硬掩模的方法。 碳掺杂的氮化硅层和UV后处理的氮化硅层对于硬掩模层具有期望的湿蚀刻速率和干蚀刻速率。

公开(公告)号：US20090093132A1

公开(公告)日：2009-04-09

申请号：US11869416

申请日：2007-10-09

申请人： HUIWEN XU ,  Yijun Liu ,  Li-Qun Xia ,  Derek R. Witty ,  Hichem M'Saad

发明人： HUIWEN XU ,  Yijun Liu ,  Li-Qun Xia ,  Derek R. Witty ,  Hichem M'Saad

IPC分类号： H01L21/31

CPC分类号： H01L21/02205 ,  C23C16/22 ,  C23C16/505 ,  H01L21/02112 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/3121 ,  H01L21/3148 ,  H01L21/3185

摘要： The present invention generally provides a method for forming a dielectric barrier with lowered dielectric constant, improved etching resistivity and good barrier property. One embodiment provides a method for processing a semiconductor substrate comprising flowing a precursor to a processing chamber, wherein the precursor comprises silicon-carbon bonds and carbon-carbon bonds, and generating a low density plasma of the precursor in the processing chamber to form a dielectric barrier film having carbon-carbon bonds on the semiconductor substrate, wherein the at least a portion of carbon-carbon bonds in the precursor is preserved in the low density plasma and incorporated in the dielectric barrier film.

摘要翻译： 本发明通常提供一种形成具有降低的介电常数，改进的蚀刻电阻率和良好的阻挡性能的介电阻挡层的方法。 一个实施例提供了一种用于处理半导体衬底的方法，包括将前体流入处理室，其中前体包含硅 - 碳键和碳 - 碳键，并在处理室中产生前体的低密度等离子体以形成电介质 在半导体衬底上具有碳 - 碳键的阻挡膜，其中前体中的至少一部分碳 - 碳键保存在低密度等离子体中并且并入介电阻挡膜中。

公开(公告)号：US20090093112A1

公开(公告)日：2009-04-09

申请号：US11869396

申请日：2007-10-09

申请人： AMIR AL-BAYATI ,  Alexandros T. Demos ,  Kang Sub Yim ,  Mehul Naik ,  Zhenjiang 'David' Cui ,  Mihaela Balseanu ,  Meiyee (Maggie Le) Shek ,  Li-Qun Xia

发明人： AMIR AL-BAYATI ,  Alexandros T. Demos ,  Kang Sub Yim ,  Mehul Naik ,  Zhenjiang 'David' Cui ,  Mihaela Balseanu ,  Meiyee (Maggie Le) Shek ,  Li-Qun Xia

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76825 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76885

摘要： A method and apparatus for generating air gaps in a dielectric material of an interconnect structure. One embodiment provides a method for forming a semiconductor structure comprising depositing a first dielectric layer on a substrate, forming trenches in the first dielectric layer, filling the trenches with a conductive material, planarizing the conductive material to expose the first dielectric layer, depositing a dielectric barrier film on the conductive material and exposed first dielectric layer, depositing a hard mask layer over the dielectric barrier film, forming a pattern in the dielectric barrier film and the hard mask layer to expose selected regions of the substrate, oxidizing at least a portion of the first dielectric layer in the selected region of the substrate, removing oxidized portion of the first dielectric layer to form reversed trenches around the conductive material, and forming air gaps in the reversed trenches while depositing a second dielectric material in the reversed trenches.

摘要翻译： 一种用于在互连结构的电介质材料中产生气隙的方法和装置。 一个实施例提供了一种用于形成半导体结构的方法，包括在衬底上沉积第一介电层，在第一介电层中形成沟槽，用导电材料填充沟槽，平坦化导电材料以暴露第一介电层， 在导电材料和暴露的第一电介质层上的阻挡膜，在介电阻挡膜上沉积硬掩模层，在介电阻挡膜和硬掩模层中形成图案，以暴露衬底的选定区域，氧化至少一部分 在衬底的选定区域中的第一介电层，去除第一电介质层的氧化部分以在导电材料周围形成反向沟槽，以及在反向沟槽中形成气隙，同时在反向沟槽中沉积第二电介质材料。

公开(公告)号：US20090087977A1

公开(公告)日：2009-04-02

申请号：US12241826

申请日：2008-09-30

申请人： MATTHEW SPULLER ,  Melody Agustin ,  Meiyee (Maggie Le) Shek ,  Li-Qun Xia ,  Reza Arghavani

发明人： MATTHEW SPULLER ,  Melody Agustin ,  Meiyee (Maggie Le) Shek ,  Li-Qun Xia ,  Reza Arghavani

IPC分类号： H01L21/3205

CPC分类号： H01L21/31608 ,  C23C16/0272 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02304 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7833

摘要： The present invention generally provides apparatus and method for processing a semiconductor substrate. Particularly, embodiments of the present invention relate to a method and apparatus for forming semiconductor devices having a conformal silicon oxide layer formed at low temperature. One embodiment of the present invention provides a method for forming a semiconductor gate structure. The method comprises forming a gate stack on a semiconductor substrate, forming a conformal silicon oxide layer on the semiconductor substrate using a low temperature cyclic method, and forming a spacer layer on the conformal silicon oxide layer.

摘要翻译： 本发明总体上提供了用于处理半导体衬底的装置和方法。 特别地，本发明的实施例涉及一种用于形成半导体器件的方法和装置，其具有在低温下形成的共形氧化硅层。 本发明的一个实施例提供一种形成半导体栅极结构的方法。 该方法包括在半导体衬底上形成栅叠层，在半导体衬底上使用低温循环法形成共形氧化硅层，并在保形氧化硅层上形成间隔层。

公开(公告)号：US20080020591A1

公开(公告)日：2008-01-24

申请号：US11762590

申请日：2007-06-13

申请人： Mihaela Balseanu ,  Victor Nguyen ,  Li-Qun Xia ,  Derek Witty ,  Hichem M'Saad ,  Mei-Yee Shek ,  Isabelita Roflox

发明人： Mihaela Balseanu ,  Victor Nguyen ,  Li-Qun Xia ,  Derek Witty ,  Hichem M'Saad ,  Mei-Yee Shek ,  Isabelita Roflox

IPC分类号： H01L21/31

CPC分类号： H01L21/3105 ,  C23C16/345 ,  C23C16/56 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3185 ,  H01L21/823807 ,  H01L29/66583 ,  H01L29/7843

摘要： Stress of a silicon nitride layer may be enhanced by deposition at higher temperatures. Employing an apparatus that allows heating of a substrate to substantially greater than 400° C. (for example a heater made from ceramic rather than aluminum), the silicon nitride film as-deposited may exhibit enhanced stress allowing for improved performance of the underlying MOS transistor device. In accordance with alternative embodiments, a deposited silicon nitride film is exposed to curing with ultraviolet (UV) radiation at an elevated temperature, thereby helping remove hydrogen from the film and increasing film stress. In accordance with still other embodiments, a silicon nitride film is formed utilizing an integrated process employing a number of deposition/curing cycles to preserve integrity of the film at the sharp corner of the underlying raised feature. Adhesion between successive layers may be promoted by inclusion of a post-UV cure plasma treatment in each cycle.

摘要翻译： 氮化硅层的应力可以通过在较高温度下沉积来增强。 使用允许将衬底加热到​​基本上大于400℃的装置（例如由陶瓷而不是铝制成的加热器），沉积的氮化硅膜可能表现出增强的应力，从而可以改善下面的MOS晶体管的性能 设备。 根据替代实施例，沉积的氮化硅膜在升高的温度下暴露于紫外线（UV）辐射固化，从而有助于从膜中除去氢并增加膜应力。 根据其他实施例，使用采用多个沉积/固化周期的整合方法形成氮化硅膜，以保持薄膜在底层凸起特征的尖角处的完整性。 可以通过在每个循环中包括UV后固化等离子体处理来促进连续层之间的粘附。