公开(公告)号：US10256188B2

公开(公告)日：2019-04-09

申请号：US15361401

申请日：2016-11-26

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal ,  Benjamin Stassen Cook ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L27/08 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L23/31 ,  H01L23/48 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/288 ,  H01L21/285 ,  H01L21/324 ,  H01L21/3105 ,  H01L23/367 ,  H01L23/373

Abstract: An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a graphitic via in the interconnect region. The graphitic via vertically connects a first interconnect in a first interconnect level to a second interconnect in a second, higher, interconnect level. The graphitic via includes a cohered nanoparticle film of nanoparticles in which adjacent nanoparticles cohere to each other, and a layer of graphitic material disposed on the cohered nanoparticle film. The nanoparticles include one or more metals suitable for catalysis of the graphitic material. The cohered nanoparticle film is formed by a method which includes an additive process. The graphitic via is electrically coupled to an active component of the integrated circuit.

公开(公告)号：US20190058232A1

公开(公告)日：2019-02-21

申请号：US15681541

申请日：2017-08-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Adam Joseph Fruehling ,  Benjamin Stassen Cook ,  Juan Alejandro Herbsommer ,  Swaminathan Sankaran

IPC: H01P5/02 ,  H01P3/12

Abstract: An apparatus includes a substrate containing a cavity and a dielectric structure covering at least a portion of the cavity. The cavity is hermetically sealed. The apparatus also may include a launch structure formed on the dielectric structure and outside the hermetically sealed cavity. The launch structure is configured to cause radio frequency (RF) energy flowing in a first direction to enter the hermetically sealed cavity through the dielectric structure in a direction orthogonal to the first direction. Various types of launch structures are disclosed herein.

公开(公告)号：US20180151463A1

公开(公告)日：2018-05-31

申请号：US15361390

申请日：2016-11-26

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal ,  Benjamin Stassen Cook ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/367 ,  H01L23/522 ,  H01L23/373 ,  H01L21/768

Abstract: An integrated circuit has a thermal routing structure above a top interconnect level. The top interconnect level includes interconnects connected to lower interconnect levels, and does not include bond pads, probe pads, input/output pads, or a redistribution layer to bump bond pads. The thermal routing structure extends over a portion, but not all, of a plane of the integrated circuit containing the top interconnect level. The thermal routing structure includes a layer of nanoparticles in which adjacent nanoparticles are attached to each other. The layer of nanoparticles is free of an organic binder material. The thermal routing structure has a thermal conductivity higher than the metal in the top interconnect level. The layer of nanoparticles is formed by an additive process.

公开(公告)号：US20180138110A1

公开(公告)日：2018-05-17

申请号：US15354137

申请日：2016-11-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Benjamin Stassen Cook

IPC: H01L23/495 ,  H01L21/48

CPC classification number: H01L23/49541 ,  B22F1/0059 ,  B22F3/1021 ,  B22F3/1025 ,  B22F3/1109 ,  B22F3/1121 ,  B22F7/004 ,  H01L21/4828 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/4951 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49555 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/49586 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00

Abstract: The surface of a substrate of a first material is modified by depositing a layer of a solvent paste comprising nanoparticles of a second material that have a size that provides a melting point at a lower temperature than the melting point temperature of the bulk second material, and nanoparticles of a third material that have a size at least as large as the nanoparticle size of the second material and a melting point at a temperature higher than the melting point temperature of the second material. Nanoparticles of the second material have a higher weight percentage than nanoparticles of the third material. The nanoparticles of the second material are sintered together at the melting point temperature of the second material. Voids are created in the layer of second material by removing the nanoparticles of the third material The voids have random distribution and random three-dimensional configurations.

公开(公告)号：US09865537B1

公开(公告)日：2018-01-09

申请号：US15395817

申请日：2016-12-30

Applicant: Texas Instruments Incorporated

Inventor： Barry Jon Male ,  Steve Kummerl ,  Benjamin Stassen Cook

IPC: H01L29/00 ,  H01L23/525 ,  H01L23/00 ,  H01L23/495 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/5256 ,  H01L21/56 ,  H01L23/315 ,  H01L23/49503 ,  H01L23/49517 ,  H01L23/562 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48245

Abstract: In described examples, an apparatus includes: an integrated circuit die having multiple terminals; the integrated circuit die positioned on a die pad portion of a leadframe having leads for external connections, at least some of the leads having an inner portion electrically coupled to at least one terminal of the integrated circuit die; a fuse element coupled between one of the leads of the leadframe and at least one terminal selected from the multiple terminals of the integrated circuit die; and encapsulation material surrounding the integrated circuit die and the leadframe to form a packaged integrated circuit including the integrated circuit die and the fuse element, and having a cavity in the encapsulation material surrounding the fuse element such that the fuse element is spaced from the encapsulation material.

公开(公告)号：US09780017B2

公开(公告)日：2017-10-03

申请号：US15346822

申请日：2016-11-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Benjamin Stassen Cook ,  Juan Alejandro Herbsommer ,  Yong Lin ,  Rongwei Zhang ,  Abram Castro ,  Matthew David Romig

IPC: H01L23/49 ,  H01L23/495 ,  H01L21/288 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/4952 ,  H01L21/2885 ,  H01L21/4821 ,  H01L21/4825 ,  H01L21/4867 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49572 ,  H01L23/49582 ,  H01L23/49586 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49883 ,  H01L24/05 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/0612 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/73265 ,  H01L2224/75 ,  H01L2224/83192 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/1511 ,  H01L2924/1711 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/0665

Abstract: A method of lead frame surface modification includes providing at least one pre-fabricated metal lead frame or package substrate (substrate) unit including a base metal having a die pad and a plurality of contact regions surrounding the die pad. An ink including a material that is a solid or a precursor for a solid that forms a solid upon a curing step or a sintering step that removes a liquid carrier is additively deposited including onto at least one of (i) a region of the die pad and (ii) at one region of at least a first of the contact regions (first contact region). The ink is sintered or cured to remove the liquid carrier so that a substantially solid ink residue remains.

公开(公告)号：US09524926B2

公开(公告)日：2016-12-20

申请号：US14848975

申请日：2015-09-09

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Juan Alejandro Herbsommer ,  Yong Lin ,  Rongwei Zhang ,  Abram Castro ,  Matthew David Romig

IPC: H01L23/49 ,  H01L23/495 ,  H01L21/288 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/4952 ,  H01L21/2885 ,  H01L21/4821 ,  H01L21/4825 ,  H01L21/4867 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49572 ,  H01L23/49582 ,  H01L23/49586 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49883 ,  H01L24/05 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/0612 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/73265 ,  H01L2224/75 ,  H01L2224/83192 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/1511 ,  H01L2924/1711 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/0665

Abstract: A method of lead frame surface modification includes providing at least one pre-fabricated metal lead frame or package substrate (substrate) unit including a base metal having a die pad and a plurality of contact regions surrounding the die pad. An ink including a material that is a solid or a precursor for a solid that forms a solid upon a curing step or a sintering step that removes a liquid carrier is additively deposited including onto at least one of (i) a region of the die pad and (ii) at one region of at least a first of the contact regions (first contact region). The ink is sintered or cured to remove the liquid carrier so that a substantially solid ink residue remains.

Abstract translation: 引线框架表面改性的方法包括提供至少一个预制金属引线框架或封装基板（基板）单元，其包括具有管芯焊盘和围绕管芯焊盘的多个接触区域的母材。 包括在固化步骤上形成固体的固体的材料或去除液体载体的烧结步骤的材料的油墨被加成沉积，其包括至少一个（i）芯片垫的区域 和（ii）在至少第一接触区域（第一接触区域）的一个区域。 油墨被烧结或固化以除去液体载体，使得残留基本上固体的油墨残余物。

公开(公告)号：US20250079340A1

公开(公告)日：2025-03-06

申请号：US18951320

申请日：2024-11-18

Applicant: Texas Instruments Incorporated

Inventor： Scott Robert Summerfelt ,  Thomas Dyer Bonifield ,  Sreeram Subramanyam Nasum ,  Peter Smeys ,  Benjamin Stassen Cook

IPC: H01L23/00 ,  H01L21/762 ,  H01L21/78 ,  H01L23/29 ,  H01L23/31 ,  H01L23/64

Abstract: In some examples, a semiconductor device comprises a substrate, a trench, and a layer of a dielectric material. The substrate includes a semiconductor material and has opposing first and second surfaces. The trench extends between the first surface and the second surface, the trench having the dielectric material. The layer of the dielectric material is on the second surface of the substrate and is contiguous with the dielectric material in the trench.

公开(公告)号：US12191554B2

公开(公告)日：2025-01-07

申请号：US17347365

申请日：2021-06-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Bichoy Bahr ,  Benjamin Stassen Cook ,  Scott R. Summerfelt

IPC: H01P3/12 ,  H01L23/31 ,  H01L25/18 ,  H05K1/18

Abstract: In some examples, a package comprises a semiconductor die having a first surface and a second surface opposing the first surface, the semiconductor die including circuitry formed in the first surface. The package includes an acoustic waveguide in the semiconductor die, the acoustic waveguide including an array of capacitors. The array of capacitors includes a transducer portion and a diffraction grating portion. The transducer portion is configured to convert signals between electrical signals and acoustic waves, and the diffraction grating portion is configured to direct the acoustic waves toward and receive the acoustic waves from the second surface.

公开(公告)号：US12148717B2

公开(公告)日：2024-11-19

申请号：US17583322

申请日：2022-01-25

Applicant: Texas Instruments Incorporated

Inventor： Scott Robert Summerfelt ,  Thomas Dyer Bonifield ,  Sreeram Subramanyam Nasum ,  Peter Smeys ,  Benjamin Stassen Cook

IPC: H01L23/00 ,  H01L21/762 ,  H01L21/78 ,  H01L23/29 ,  H01L23/31 ,  H01L23/64

Abstract: In described examples of an integrated circuit (IC) there is a substrate of semiconductor material having a first region with a first transistor formed therein and a second region with a second transistor formed therein. An isolation trench extends through the substrate and separates the first region of the substrate from the second region of the substrate. An interconnect region having layers of dielectric is disposed on a top surface of the substrate. A dielectric polymer is disposed in the isolation trench and in a layer over the backside surface of the substrate. An edge of the polymer layer is separated from the perimeter edge of the substrate by a space.