公开(公告)号：US12068162B2

公开(公告)日：2024-08-20

申请号：US17874670

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ya-Lan Chang ,  Ting-Gang Chen ,  Tai-Chun Huang ,  Chi On Chui ,  Yung-Cheng Lu

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/28123 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/31053 ,  H01L21/76227 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: An embodiment includes a method including forming an opening in a cut metal gate region of a metal gate structure of a semiconductor device, conformally depositing a first dielectric layer in the opening, conformally depositing a silicon layer over the first dielectric layer, performing an oxidation process on the silicon layer to form a first silicon oxide layer, filling the opening with a second silicon oxide layer, performing a chemical mechanical polishing on the second silicon oxide layer and the first dielectric layer to form a cut metal gate plug, the chemical mechanical polishing exposing the metal gate structure of the semiconductor device, and forming a first contact to a first portion of the metal gate structure and a second contact to a second portion of the metal gate structure, the first portion and the second portion of the metal gate structure being separated by the cut metal gate plug.

公开(公告)号：US12051735B2

公开(公告)日：2024-07-30

申请号：US17664479

申请日：2022-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Gang Chen ,  Tai-Chun Huang ,  Ming-Chang Wen ,  Shu-Yuan Ku ,  Fu-Kai Yang ,  Tze-Liang Lee ,  Yung-Cheng Lu ,  Yi-Ting Fu

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/31116 ,  H01L21/76224 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes forming a first and a second dummy gate stack crossing over a semiconductor region, forming an ILD to embed the first and the second dummy gate stacks therein, replacing the first and the second dummy gate stacks with a first and a second replacement gate stack, respectively, performing a first etching process to form a first opening. A portion of the first replacement gate stack and a portion of the second replacement gate stack are removed. The method further includes filling the first opening to form a dielectric isolation region, performing a second etching process to form a second opening, with the ILD being etched, and the dielectric isolation region being exposed to the second opening, forming a contact spacer in the second opening, and filling a contact plug in the second opening. The contact plug is between opposite portions of the contact spacer.

公开(公告)号：US20240204104A1

公开(公告)日：2024-06-20

申请号：US18591730

申请日：2024-02-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Yu-Cheng Shiau ,  Chunyao Wang ,  Chih-Tang Peng ,  Yung-Cheng Lu ,  Chi On Chui

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/0214 ,  H01L21/02211 ,  H01L21/02263 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/0924 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66818 ,  H01L21/76227

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a first liner is deposited to line a recess between a first semiconductor fin and a second semiconductor fin, the first liner comprising a first material. The first liner is annealed to transform the first material to a second material. A second liner is deposited to line the recess, the second liner comprising a third material. The second liner is annealed to transform the third material to a fourth material.

公开(公告)号：US12002719B2

公开(公告)日：2024-06-04

申请号：US18083757

申请日：2022-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-En Lin ,  Chi On Chui ,  Fang-Yi Liao ,  Chunyao Wang ,  Yung-Cheng Lu

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/762 ,  H01L21/764 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823878 ,  H01L21/28088 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method includes patterning a trench and depositing a first insulating material along sidewalls and a bottom surface of the trench using a conformal deposition process. Depositing the first insulating material includes forming a first seam between a first portion of the first insulating material on a first sidewall of the trench and a second portion of the first insulating material on a second sidewall of the trench. The method further includes etching the first insulating material below a top of the trench and depositing a second insulating material over the first insulating material and in the trench using a conformal deposition process. Depositing the second insulating material comprises forming a second seam between a first portion of the second insulating material on the first sidewall of the trench and a second portion of the second insulating material on a second sidewall of the trench.

公开(公告)号：US11942549B2

公开(公告)日：2024-03-26

申请号：US18064562

申请日：2022-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Yu-Cheng Shiau ,  Chunyao Wang ,  Chih-Tang Peng ,  Yung-Cheng Lu ,  Chi On Chui

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/0214 ,  H01L21/02211 ,  H01L21/02263 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/0924 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66818 ,  H01L21/76227

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a first liner is deposited to line a recess between a first semiconductor fin and a second semiconductor fin, the first liner comprising a first material. The first liner is annealed to transform the first material to a second material. A second liner is deposited to line the recess, the second liner comprising a third material. The second liner is annealed to transform the third material to a fourth material.

公开(公告)号：US11923432B2

公开(公告)日：2024-03-05

申请号：US18149224

申请日：2023-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yoh-Rong Liu ,  Wen-Kai Lin ,  Che-Hao Chang ,  Chi On Chui ,  Yung-Cheng Lu ,  Li-Chi Yu ,  Sen-Hong Syue

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/66553 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78696

Abstract: A method of manufacturing a semiconductor device includes forming a multi-layer stack of alternating first layers of a first semiconductor material and second layers of a second semiconductor material on a semiconductor substrate, forming a first recess through the multi-layer stack, and laterally recessing sidewalls of the second layers of the multi-layer stack. The sidewalls are adjacent to the first recess. The method further includes forming inner spacers with respective seams adjacent to the recessed second layers of the multi-layer stack and performing an anneal treatment on the inner spacers to close the respective seams.

公开(公告)号：US11865666B2

公开(公告)日：2024-01-09

申请号：US18067960

申请日：2022-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Chien Hou ,  Ching-Hong Jiang ,  Kuo-Yin Lin ,  Ming-Shiuan She ,  Shen-Nan Lee ,  Teng-Chun Tsai ,  Yung-Cheng Lu

IPC: B24B37/32 ,  B24B37/20 ,  B24B37/04

CPC classification number: B24B37/20 ,  B24B37/042 ,  B24B37/32

Abstract: An apparatus for performing chemical mechanical polish on a wafer includes a polishing head that includes a retaining ring. The polishing head is configured to hold the wafer in the retaining ring. The retaining ring includes a first ring having a first hardness, and a second ring encircled by the first ring, wherein the second ring has a second hardness smaller than the first hardness.

公开(公告)号：US11764221B2

公开(公告)日：2023-09-19

申请号：US17157182

申请日：2021-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Hung Cheng Lin ,  Chunyao Wang ,  Yung-Cheng Lu ,  Chi On Chui

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a dielectric fin is formed in order to help isolate adjacent semiconductor fins. The dielectric fin is formed using a deposition process in which deposition times and temperatures are utilized to increase the resistance of the dielectric fin to subsequent etching processes.

公开(公告)号：US11757020B2

公开(公告)日：2023-09-12

申请号：US16941445

申请日：2020-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Che-Hao Chang ,  Yung-Cheng Lu ,  Chi On Chui

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/336 ,  H01L29/66 ,  H01L21/02 ,  H01L29/417 ,  H01L21/385 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092

CPC classification number: H01L29/66795 ,  H01L21/0228 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/7851 ,  H01L21/385 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/785

Abstract: A method includes forming a fin extending from a substrate; forming an first isolation region along opposing sidewalls of the fin; forming a gate structure over the fin; forming an epitaxial source/drain region in the fin adjacent the gate structure; forming an etch stop layer over the epitaxial source/drain region and over the gate structure; forming a protection layer over the etch stop layer, the protection layer including silicon oxynitride; and forming a second isolation material over the protection layer, wherein forming the second isolation material reduces a nitrogen concentration of the protection layer.

公开(公告)号：US20230275140A1

公开(公告)日：2023-08-31

申请号：US18303841

申请日：2023-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kai Lin ,  Yung-Cheng Lu ,  Che-Hao Chang ,  Chi On Chui

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8234

CPC classification number: H01L29/66553 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/4983 ,  H01L29/78618 ,  H01L29/66742 ,  H01L21/0259 ,  H01L21/31116 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/78696 ,  H01L21/823431 ,  H01L29/66795

Abstract: A method of forming a semiconductor device includes: forming a dummy gate structure over a nanostructure, where the nanostructure overlies a fin that protrudes above a substrate, where the nanostructure comprises alternating layers of a first semiconductor material and a second semiconductor material; forming openings in the nanostructure on opposing sides of the dummy gate structure, the openings exposing end portions of the first semiconductor material and end portions of the second semiconductor material; recessing the exposed end portions of the first semiconductor material to form first sidewall recesses; filling the first sidewall recesses with a multi-layer spacer film; removing at least one sublayer of the multi-layer spacer film to form second sidewall recesses; and forming source/drain regions in the openings after removing at least one sublayer, where the source/drain regions seal the second sidewall recesses to form sealed air gaps.