公开(公告)号：US20090033773A1

公开(公告)日：2009-02-05

申请号：US11665037

申请日：2006-08-09

申请人： Hiroyuki Kinoshita ,  Jing Zhang ,  Masahiro Ito ,  Akira Matsui

发明人： Hiroyuki Kinoshita ,  Jing Zhang ,  Masahiro Ito ,  Akira Matsui

IPC分类号： H04N5/217 ,  G06K9/40 ,  H04N5/00

CPC分类号： H04N5/21 ,  G06T3/4023 ,  G06T5/002 ,  G06T5/005 ,  G06T5/20 ,  G06T7/13 ,  G06T2207/10024 ,  G06T2207/20012 ,  G06T2207/20032 ,  G06T2207/20192 ,  H04N5/213

摘要： Noise reduction is performed on the basis of characteristics of an image in a detection range. A noise reduction block 4′ performs a second-order differentiation process and a symmetry process to decide adjacent pixels with which noise reduction is preformed for an attention pixel. With the pixel level of the attention pixel in the detection range and the pixel levels of adjacent pixels used for noise reduction, an arithmetic mean processing section 16 calculates a mean value. A median filter 17 selects a median value. With the number of pixels used for noise reduction, it is determined whether the image in the detection range contains a flat portion, a ramp portion, or an edge. The mean value and the median value are weight-added with a weighted coefficient that are changed on the basis of characteristics of the image. The result is substituted for the level of the attention pixel. When the attention pixel is an isolated point, an all-pixel median filter section 31 selects a medium value of the levels of all the pixels in the detection range including the attention pixel and substitutes the median value for the level of the attention pixel.

摘要翻译： 基于检测范围内的图像的特性进行降噪。 降噪块4'执行二阶微分处理和对称处理，以确定针对注意像素执行降噪的相邻像素。 利用检测范围内的关注像素的像素级和用于降噪的相邻像素的像素级，算术平均处理部16计算平均值。 中值滤波器17选择中值。 利用用于降噪的像素数量，确定检测范围内的图像是否包含平坦部分，斜坡部分或边缘。 平均值和中值是加权系数，加权系数根据图像的特性而改变。 结果代替注意像素的级别。 当注意像素是孤立点时，全像素中值滤波器部分31选择包括关注像素在内的检测范围内的所有像素的电平的中值，并代入关注像素的电平的中值。

公开(公告)号：US20080268650A1

公开(公告)日：2008-10-30

申请号：US11742003

申请日：2007-04-30

申请人： Chungho Lee ,  Huaqiang Wu ,  Wai Lo ,  Hiroyuki Kinoshita

发明人： Chungho Lee ,  Huaqiang Wu ,  Wai Lo ,  Hiroyuki Kinoshita

IPC分类号： H01L21/302

CPC分类号： H01L27/11573 ,  H01L21/28282

摘要： A method of replacing a top oxide around a storage element of a memory device is provided. The method can involve removing a core first poly and core first top oxide in a core region while not removing a periphery first poly in a periphery region on a semiconductor substrate; forming a second top oxide around a storage element in the core region and on the periphery first poly in the periphery region; forming a second poly over the semiconductor substrate in both the core and periphery regions; removing the second poly and second top oxide in the periphery region; and forming a third poly on the semiconductor substrate in both the core and periphery regions.

摘要翻译： 提供了替换存储器件的存储元件周围的顶部氧化物的方法。 该方法可以包括在核心区域中去除核心的第一多核和第一顶部氧化物，而不去除半导体衬底上的外围区域中的周边第一多晶硅; 在所述芯区域中的存储元件周围和所述周边区域的所述外围第一聚四氟乙烯上形成第二顶部氧化物; 在所述芯和外围区域中在所述半导体衬底上形成第二聚合物; 去除所述周边区域中的所述第二聚合物和第二顶部氧化物; 以及在所述芯和外围区域中在所述半导体衬底上形成第三聚合物。

公开(公告)号：US07242102B2

公开(公告)日：2007-07-10

申请号：US10887585

申请日：2004-07-08

申请人： Inkuk Kang ,  Hiroyuki Kinoshita ,  Boon-Yong Ang ,  Hajime Wada ,  Simon S Chan ,  Cinti X Chen

发明人： Inkuk Kang ,  Hiroyuki Kinoshita ,  Boon-Yong Ang ,  Hajime Wada ,  Simon S Chan ,  Cinti X Chen

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/28

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L2224/02166 ,  H01L2224/05073 ,  H01L2224/05147 ,  H01L2224/05181 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/05042

摘要： According to one exemplary embodiment, a structure in a semiconductor die comprises a metal pad situated in an interconnect metal layer, where the metal pad comprises copper. The structure further comprises an interlayer dielectric layer situated over the metal pad. The structure further comprises a terminal via defined in the interlayer dielectric layer, where the terminal via is situated on the metal pad. The terminal via extends along only one side of the metal pad. The structure further comprises a terminal metal layer situated on the interlayer dielectric layer and in the terminal via. The structure further comprises a dielectric liner situated on the terminal metal layer, where a bond pad opening is defined in the dielectric liner, and where the bond pad opening exposes a portion of the terminal metal layer. The interlayer dielectric layer is situated between the exposed portion of the terminal metal layer and metal pad.

摘要翻译： 根据一个示例性实施例，半导体管芯中的结构包括位于互连金属层中的金属焊盘，其中金属焊盘包括铜。 该结构还包括位于金属焊盘上的层间电介质层。 该结构还包括限定在层间电介质层中的端子通孔，其中端子通孔位于金属焊盘上。 端子通孔仅沿着金属焊盘的一侧延伸。 该结构还包括位于层间电介质层和端子通孔中的端子金属层。 所述结构还包括位于所述端子金属层上的电介质衬垫，其中所述电介质衬垫中限定了焊盘开口，并且所述接合焊盘开口露出所述端子金属层的一部分。 层间绝缘层位于端子金属层的暴露部分和金属焊盘之间。

公开(公告)号：US07202540B2

公开(公告)日：2007-04-10

申请号：US11066567

申请日：2005-02-28

申请人： Hideki Komori ,  Hisayuki Shimada ,  Yu Sun ,  Hiroyuki Kinoshita

发明人： Hideki Komori ,  Hisayuki Shimada ,  Yu Sun ,  Hiroyuki Kinoshita

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/11521 ,  H01L21/823425 ,  H01L21/823468 ,  H01L27/115 ,  H01L27/11568 ,  Y10S257/90

摘要： A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped impurity region (7b) to reduce the contact resistance at the drain (7).

摘要翻译： 漏极（7）包括与控制栅极（5）对准的轻掺杂浅杂质区域（7a）和与侧壁膜（8）对准并掺杂杂质的重掺杂深杂质区域（7b） 其浓度高于轻掺杂浅杂质区（7a）的浓度。 轻掺杂的浅杂质区域（7a）导致短沟道效应和编程效率的改善。 漏极接触孔形成部分（70）设置到重掺杂杂质区域（7b）以降低漏极（7）处的接触电阻。

公开(公告)号：US20060102924A1

公开(公告)日：2006-05-18

申请号：US10525753

申请日：2003-08-21

申请人： Shigeki Otani ,  Hiroyuki Kinoshita ,  Hiroyuki Matsunami ,  Jun Suda ,  Hiroshi Amano ,  Isamu Akasaki ,  Satoshi Kamiyama

发明人： Shigeki Otani ,  Hiroyuki Kinoshita ,  Hiroyuki Matsunami ,  Jun Suda ,  Hiroshi Amano ,  Isamu Akasaki ,  Satoshi Kamiyama

IPC分类号： H01L33/00

CPC分类号： H01L31/0264 ,  C30B29/10 ,  C30B33/00 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/0254 ,  H01L29/045 ,  H01L29/24 ,  H01S5/0213 ,  H01S5/0218 ,  H01S5/32341

摘要： Disclosed are a diboride single crystal substrate which has a cleavage plane as same as that of a nitride compound semiconductor and is electrically conductive; a semiconductor laser diode and a semiconductor device using such a substrate and methods of their manufacture wherein the substrate is a single crystal substrate 1 of diboride XB2 (where X is either Zr or Ti) which is facially oriented in a (0001) plane 2 and has a thickness of 0.1 mm or less. The substrate 1 is permitted cleaving and splitting along a (10-10) plane 4 with ease. Using this substrate to form a semiconductor laser diode of a nitride compound, a vertical structure device can be realized. Resonant planes of a semiconductor laser diode with a minimum of loss can be fabricated by splitting the device in a direction parallel to the (10-10) plane. A method of manufacture that eliminates a margin of cutting is also realized.

摘要翻译： 公开了具有与氮化物化合物半导体相同的解理面并具有导电性的二硼化物单晶基板; 半导体激光二极管和使用这种衬底的半导体器件及其制造方法，其中衬底是面向取向的二硼化物XB 2 N（其中X是Zr或Ti）的单晶衬底1 在（0001）面2中，具有0.1mm以下的厚度。 允许衬底1容易地沿着（10-10）平面4进行切割和分割。 使用该基板形成氮化物化合物的半导体激光二极管，可以实现垂直结构装置。 具有最小损耗的半导体激光二极管的谐振平面可以通过在与（10-10）平面平行的方向上分割器件来制造。 还实现了消除切割余量的制造方法。

公开(公告)号：US20060091402A1

公开(公告)日：2006-05-04

申请号：US11258998

申请日：2005-10-27

申请人： Hiromu Shiomi ,  Hiroyuki Kinoshita

发明人： Hiromu Shiomi ,  Hiroyuki Kinoshita

IPC分类号： H01L31/0312

CPC分类号： C30B29/36 ,  C30B23/00 ,  Y10S438/931

摘要： SiC single crystal that includes a first dopant functioning as an acceptor, and a second dopant functioning as a donor is provided, where the content of the first dopant is no less than 5×1015 atoms/cm3, the content of the second dopant is no less than 5×1015 atoms/cm3, and the content of the first dopant is greater than the content of the second dopant. A manufacturing method for silicon carbide single crystal is provided with the steps of: fabricating a raw material by mixing a metal boride with a material that includes carbon and silicon; vaporizing the raw material; generating a mixed gas that includes carbon, silicon, boron and nitride; and growing silicon carbide single crystal that includes boron and nitrogen on a surface of a seed crystal substrate by re-crystallizing the mixed gas on the surface of the seed crystal substrate.

摘要翻译： 提供包括用作受体的第一掺杂剂和用作供体的第二掺杂剂的SiC单晶，其中第一掺杂剂的含量不小于5×10 15原子/ 3，第二掺杂剂的含量不小于5×10 15原子/ cm 3，第一掺杂剂的含量大于 第二掺杂剂。 提供了一种碳化硅单晶的制造方法，其特征在于：通过将金属硼化物与包含碳和硅的材料混合来制造原料; 蒸发原料; 产生包括碳，硅，硼和氮化物的混合气体; 以及通过使晶种基板的表面上的混合气体再结晶，在晶种基板的表面上生长包含硼和氮的碳化硅单晶。

公开(公告)号：US20050101148A1

公开(公告)日：2005-05-12

申请号：US10705631

申请日：2003-11-08

申请人： Dawn Hopper ,  Hiroyuki Kinoshita ,  Christy Woo

发明人： Dawn Hopper ,  Hiroyuki Kinoshita ,  Christy Woo

IPC分类号： H01L21/768 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/76844 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76865

摘要： According to one exemplary embodiment, a method for forming a contact over a silicide layer situated in a semiconductor die comprises a step of depositing a barrier layer on sidewalls of a contact hole and on a native oxide layer situated at a bottom of the contact hole, where the sidewalls are defined by the contact hole in a dielectric layer. The step of depositing the barrier layer on the sidewalls of the contact hole and on the native oxide layer can be optimized such that the barrier layer has a greater thickness at a top of the contact hole than a thickness at the bottom of the contact hole. According to this exemplary embodiment, the method further comprises a step of removing a portion of the barrier layer and the native oxide layer situated at the bottom of the contact hole to expose the silicide layer.

摘要翻译： 根据一个示例性实施例，用于在位于半导体管芯中的硅化物层上形成接触的方法包括在接触孔的侧壁和位于接触孔的底部的自然氧化物层上沉积阻挡层的步骤， 其中侧壁由电介质层中的接触孔限定。 可以优化将阻挡层沉积在接触孔的侧壁和自然氧化物层上的步骤，使得阻挡层在接触孔的顶部具有比接触孔底部的厚度更大的厚度。 根据该示例性实施例，该方法还包括去除位于接触孔底部的阻挡层和自然氧化物层的一部分以露出硅化物层的步骤。

公开(公告)号：US06855608B1

公开(公告)日：2005-02-15

申请号：US10463643

申请日：2003-06-17

申请人： Mark Ramsbey ,  Mark W. Randolph ,  Jean Yee-Mei Yang ,  Hiroyuki Kinoshita ,  Cyrus Tabery ,  Jeff P. Erhardt ,  Tazrien Kamal ,  Jaeyong Park ,  Emmanuil H. Lingunis

发明人： Mark Ramsbey ,  Mark W. Randolph ,  Jean Yee-Mei Yang ,  Hiroyuki Kinoshita ,  Cyrus Tabery ,  Jeff P. Erhardt ,  Tazrien Kamal ,  Jaeyong Park ,  Emmanuil H. Lingunis

IPC分类号： G11C16/04 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/105

CPC分类号： H01L27/11568 ,  G11C16/0475 ,  G11C16/0491 ,  H01L27/105 ,  H01L27/11573

摘要： A method of fabricating a planar architecture charge trapping dielectric memory cell array with rectangular gates comprises fabricating a multi-layer charge trapping dielectric on the surface of a substrate. The layer adjacent to the substrate may be an oxide. A polysilicon layer is deposited over the charge trapping dielectric. A word line mask is applied over the polysilicon layer to mask linear word lines in a first direction and to expose trench regions there between and the trenches are etched to expose the charge trapping dielectric in the trench regions. A bit line mask is applied over the polysilicon layer to mask gates in a second direction perpendicular to the first direction and to expose bit line regions there between and the bit lines are etched to expose the oxide in the bit line regions. The bit lines are implanted and insulating spacers are fabricated on exposed sidewalls. The oxide is removed to expose the substrate between insulating spacers in the bit line regions and a conductor is fabricated thereon to enhance conductivity of each bit line.

摘要翻译： 制造具有矩形栅极的平面架构电荷俘获介质存储单元阵列的方法包括在衬底的表面上制造多层电荷俘获电介质。 与衬底相邻的层可以是氧化物。 在电荷捕获电介质上沉积多晶硅层。 在多晶硅层上施加字线掩模以在第一方向上屏蔽线性字线并且在其间露出沟槽区域，并且蚀刻沟槽以暴露沟槽区域中的电荷俘获电介质。 将位线掩模施加在多晶硅层上以在垂直于第一方向的第二方向上屏蔽栅极，并在其间暴露位线区域，并蚀刻位线以暴露位线区域中的氧化物。 植入位线，并在暴露的侧壁上制造绝缘间隔物。 去除氧化物以在位线区域中的绝缘间隔物之间​​露出衬底，并且在其上制造导体以增强每个位线的导电性。

公开(公告)号：US06809010B1

公开(公告)日：2004-10-26

申请号：US08808315

申请日：1997-02-28

申请人： Hiroyuki Kinoshita ,  Motohiro Umehara

发明人： Hiroyuki Kinoshita ,  Motohiro Umehara

IPC分类号： H01L2178

CPC分类号： H01S5/32341 ,  C30B29/20 ,  C30B33/00 ,  G02B1/02 ,  H01S5/0202 ,  H01S5/0213 ,  H01S5/0422 ,  H01S5/3202

摘要： The present invention relates to a sapphire monocrystalline body to be used as the substrate for a semiconductor for electronic parts or component parts, and to a monocrystalline sapphire substrate. The invention also relates to a method for working the same. The invention is based cleavage along the plane R of the sapphire monocrystalline body which cleavage is easy to accomplish and provides a surface high in precision. The inventive process includes forming linear crack parallel or vertical to a reference plane of the substrate, with a microcrack line as a starting point, to develop a crack in a thickness direction of the body.

摘要翻译： 本发明涉及用作电子部件或组件的半导体用基板和单晶蓝宝石基板的蓝宝石单晶体。 本发明还涉及其工作方法。 本发明是沿着蓝宝石单晶体的平面R进行的切割，其切割容易实现并提供高精度的表面。 本发明的方法包括以微裂纹线为起点形成平行或垂直于基片的参考平面的线性裂纹，以在本体的厚度方向上形成裂缝。

公开(公告)号：US06363068B1

公开(公告)日：2002-03-26

申请号：US09098907

申请日：1998-06-17

申请人： Hiroyuki Kinoshita

发明人： Hiroyuki Kinoshita

IPC分类号： H04L1228

CPC分类号： H04L12/4625

摘要： A bridge that can effectively use plural paths by restricting a single path by a spanning tree algorithm, thus preventing that a broadcast packet is circulated in a looped communication path when two neighbor brides configuring a spanning tree are physically connected with plural paths. The bridge incorporates a correspondence table for the correspondence between the transmission source Mac address and the transmission destination port of a packet. A transmission source Mac address registration section decides the transmission destination port of a packet to be transmitted from the port to other bridge. The transmission destination port is cataloged on the table. When the transmission packet is a broadcast packet or BPDU packet, it is divided to a specific port among ports of the bridge. Other packets are divided to the corresponding ports by referring to the content cataloged on the table. Thus all the paths can be effectively used.

摘要翻译： 一种可以通过生成树算法限制单个路径有效地使用多个路径的桥，从而防止当配置生成树的两个邻居新娘与多个路径物理连接时，广播包在循环通信路径中循环。 桥接器包括用于发送源Mac地址和分组的发送目的地端口之间的对应关系的对应表。 发送源Mac地址注册部分确定要从该端口发送到另一个桥的分组的发送目的地端口。 传输目标端口在表上编目。 当传输分组是广播分组或BPDU分组时，它被划分到网桥的端口中的特定端口。 其他数据包通过参考表上编目的内容划分为相应的端口。 因此，可以有效地使用所有的路径。