公开(公告)号：US4466008A

公开(公告)日：1984-08-14

申请号：US312811

申请日：1981-10-19

申请人： Heinz Beneking

发明人： Heinz Beneking

IPC分类号： H01L29/812 ,  H01L29/80 ,  H01L29/48

CPC分类号： H01L29/8122

摘要： A field effect transistor having a source and drain region arranged vertically in a semi-conductor body with an insulating layer separating them, a rectifying metal/semiconductor contact on a side surface of the semiconductor body to form a gate electrode, and a thin conductive layer arranged on the side surface to bridge the insulating layer at least in the region beneath the gate electrode.

摘要翻译： 一种场效应晶体管，其源极和漏极区域垂直布置在半导体体中，绝缘层分离，半导体本体的侧表面上的整流金属/半导体接触以形成栅电极，以及薄导电层 布置在侧表面上至少在栅电极下方的区域中桥接绝缘层。

公开(公告)号：US4343015A

公开(公告)日：1982-08-03

申请号：US149936

申请日：1980-05-14

申请人： Bantval J. Baliga ,  James R. Shealy

发明人： Bantval J. Baliga ,  James R. Shealy

IPC分类号： H01L21/338 ,  H01L29/10 ,  H01L29/423 ,  H01L29/812

CPC分类号： H01L29/66856 ,  H01L29/1025 ,  H01L29/42316 ,  H01L29/8122

摘要： Improved high frequency GaAs FETs have a higher breakdown voltage, lower input gate capacitance and lower source (or drain) resistance. A preferentially etched groove structure yields parallel trapezoidal semiconductor fingers that are wider at the top than at the bottom. Every finger intersects a high resistivity, semi-insulating region which surrounds the active device area and is fabricated by high energy particle bombardment. Metal gates are deposited within the grooves on three sides of the trapezoidal fingers.

摘要翻译： 改进的高频GaAs FET具有更高的击穿电压，较低的输入栅极电容和较低的源极（或漏极）电阻。 优先蚀刻的凹槽结构产生在顶部比底部更宽的平行梯形半导体指状物。 每个指状物与围绕有源器件区域的高电阻率半绝缘区域相交，并且通过高能量粒子轰击制造。 金属门沉积在梯形手指三侧的槽内。

公开(公告)号：US4249190A

公开(公告)日：1981-02-03

申请号：US54822

申请日：1979-07-05

申请人： Alfred Y. Cho

发明人： Alfred Y. Cho

IPC分类号： H01L29/417 ,  H01L21/203 ,  H01L21/285 ,  H01L21/338 ,  H01L29/47 ,  H01L29/80 ,  H01L29/812 ,  H01L29/872

CPC分类号： H01L29/66856 ,  H01L21/02395 ,  H01L21/02463 ,  H01L21/02546 ,  H01L21/02631 ,  H01L21/28581 ,  H01L29/8122

摘要： A planar field effect transistor (FET) includes a plurality of spaced-apart, floating Schottky barrier, epitaxial metal gate electrodes which are embedded within a semiconductor body. A drain electrode and a gate control electrode are formed on one major surface of the body whereas a source electrode, typically grounded, is formed on an opposite major surface of the body. The FET channel extends vertically between the source and drain, and current flow therein is controlled by application of suitable gate voltage. Two modes of operation are possible: (1) the depletion regions of the control gates and the floating gates pinch off the channel so that with zero control gate voltage no current flows from source to drain; then, forward biasing the control gate opens the channel; and (2) the depletion regions of the control gates and the floating gates do not pinch off the channel, but reverse biasing the control gate produces pinch off. Specifically described is a GaAs FET in which the floating gate electrodes are Al epitaxial layers grown by molecular beam epitaxy.

摘要翻译： 平面场效应晶体管（FET）包括多个间隔开的浮动肖特基势垒，嵌入在半导体本体内的外延金属栅电极。 漏极电极和栅极控制电极形成在主体的一个主表面上，而通常接地的源电极形成在主体的相对主表面上。 FET通道在源极和漏极之间垂直延伸，并且通过施加合适的栅极电压来控制其中的电流。 两种操作模式是可能的：（1）控制栅极和浮栅的耗尽区夹紧通道，使得在零控制栅极电压下，没有电流从源极流到漏极; 然后，正向偏置控制门打开通道; 和（2）控制栅极和浮置栅极的耗尽区不夹断沟道，而反向偏置控制栅极会产生夹断。 具体描述的是其中浮栅电极是通过分子束外延生长的Al外延层的GaAs FET。

公开(公告)号：US4236166A

公开(公告)日：1980-11-25

申请号：US54821

申请日：1979-07-05

申请人： Alfred Y. Cho ,  James V. DiLorenzo

发明人： Alfred Y. Cho ,  James V. DiLorenzo

IPC分类号： H01L29/06 ,  H01L29/12 ,  H01L29/205 ,  H01L29/78 ,  H01L29/80 ,  H01L29/812

CPC分类号： H01L29/7828 ,  H01L29/8122

摘要： A vertical field effect transistor (10) includes a relatively wide bandgap, lowly doped active layer (18) epitaxially grown on, and substantially lattice matched to, an underlying semiconductor body portion (13). A mesa (20) of lower bandgap material is epitaxially grown on and substantially lattice matched to the active layer. A source electrode (22) is formed on a bottom major surface (34) of the semiconductor body portion, a drain electrode (24) is formed on the top of the mesa, and a pair of gate electrode stripes (26) are formed on the active layer adjacent both sides of the mesa. When voltage (V.sub.G), negative with respect to the drain, is applied to the gate electrodes, the depletion regions (28) thereunder extend laterally in the active layer until they intersect, thereby pinching off the flow of current in the channel extending from the drain and source electrodes. Also described is an embodiment in which spaced-apart, high impedance zones (30) underlie the active layer and the mesas, and the spaces between zones underlie the gate stripes.

摘要翻译： 垂直场效应晶体管（10）包括在下面的半导体主体部分（13）上外延生长并基本上与其基本上晶格匹配的相对较宽的带隙低掺杂有源层（18）。 较低带隙材料的台面（20）外延生长并基本上与有源层晶格匹配。 源电极（22）形成在半导体主体部分的底部主表面（34）上，在台面的顶部形成漏极电极（24），并且一对栅电极条（26）形成在 邻近台面两侧的活动层。 当相对于漏极的负电压（VG）被施加到栅电极时，其下面的耗尽区（28）在有源层中横向延伸，直到它们相交，从而夹紧从沟道延伸的通道中的电流 漏极和源极。 还描述了一种实施例，其中位于有源层和台面之下的间隔开的高阻抗区域（30）以及位于栅极条之下的区域之间的空间。

公开(公告)号：US4129879A

公开(公告)日：1978-12-12

申请号：US908508

申请日：1978-05-22

申请人： Wirojana Tantraporn ,  Se P. Yu

发明人： Wirojana Tantraporn ,  Se P. Yu

IPC分类号： H01L29/78 ,  H01L29/812 ,  H01L29/80

CPC分类号： H01L29/7827 ,  H01L29/8122

摘要： An interdigitated field effect transistor for high power, high frequency applications has a vertical configuration with current flow essentially normal to the surface, as compared to planar devices in which current flow is parallel to the surface. Each channel region is of the same conductivity type as the source and drain regions and is in a mesa structure surrounded by the gate metallization such that the gate metal forms an electronically blocking contact to the channel semiconductor. The device geometry has a natural strip line configuration.

摘要翻译： 与电流平行于表面的平面器件相比，用于高功率，高频应用的交叉指向的场效应晶体管具有垂直配置，其电流基本上垂直于表面。 每个沟道区具有与源极和漏极区相同的导电类型，并且是由栅极金属化包围的台面结构，使得栅极金属形成与沟道半导体的电子阻挡接触。 设备几何具有自然的带状线配置。

公开(公告)号：US12107167B2

公开(公告)日：2024-10-01

申请号：US17762929

申请日：2021-01-20

申请人： SOUTHEAST UNIVERSITY

发明人： Siyang Liu ,  Weifeng Sun ,  Chi Zhang ,  Shuxuan Xin ,  Shen Li ,  Le Qian ,  Chen Ge ,  Longxing Shi

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/778 ,  H01L29/812

CPC分类号： H01L29/7851 ,  H01L29/1095 ,  H01L29/778 ,  H01L29/8122

摘要： The present invention discloses a high-threshold power semiconductor device and a manufacturing method thereof. The high-threshold power semiconductor device includes, in sequence from bottom to top: a metal drain electrode, a substrate, a buffer layer, and a drift region; further including: a composite column body which is jointly formed by a drift region protrusion, a columnar p-region and a columnar n-region on the drift region, a channel layer, a passivation layer, a dielectric layer, a heavily doped semiconductor layer, a metal gate electrode and a source metal electrode. The composite column body is formed by sequentially depositing a p-type semiconductor layer and an n-type semiconductor layer on the drift region and then etching same. The channel layer and the passivation layer are formed in sequence by deposition. Thus, the above devices are divided into a cell region and a terminal region. The dielectric layer, the heavily doped semiconductor layer, the metal gate electrode and the source metal electrode only exist in the cell region, and the passivation layer of the terminal region extends upwards and is wrapped outside the channel layer. This structure can increase a threshold voltage of the device, improve the blocking characteristics of the device and reduce the size of a gate capacitance.

公开(公告)号：US20170352757A1

公开(公告)日：2017-12-07

申请号：US15613707

申请日：2017-06-05

申请人： Alfred I. Grayzel

发明人： Alfred I. Grayzel

IPC分类号： H01L29/78 ,  H01L27/06 ,  H01L29/10 ,  H01L29/812 ,  H01L29/808

CPC分类号： H01L29/7831 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/1045 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/808 ,  H01L29/8083 ,  H01L29/8122 ,  H01L29/8124

摘要： A Field Effect Transistor including: a channel with one end designated the source and the other end designated the drain; a means for connecting to said source end of said channel; a means for connecting to said drain end of said channel; a gate divided into a plurality of segments each insulated from one another; a means for adjusting the bias of each of said segments independently of one another, whereby the depletion region in said channel can be adjusted to avoid pinch-off and to maximize the efficiency of said Field Effect Transistor.

公开(公告)号：US09466481B2

公开(公告)日：2016-10-11

申请号：US14329730

申请日：2014-07-11

申请人： SixPoint Materials, Inc. ,  Seoul Semiconductor Co., Ltd.

发明人： Tadao Hashimoto

IPC分类号： H01L29/20 ,  H01L21/02 ,  H01L29/207 ,  H01L29/78 ,  H01L29/812 ,  C23C16/30 ,  H01L29/861 ,  H01L29/872 ,  H01L29/201 ,  H01L29/417 ,  H01L29/06 ,  H01L29/205

CPC分类号： H01L21/0254 ,  C23C16/303 ,  H01L21/02389 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/02584 ,  H01L21/0262 ,  H01L21/02623 ,  H01L21/02694 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/207 ,  H01L29/32 ,  H01L29/41766 ,  H01L29/66462 ,  H01L29/7784 ,  H01L29/7828 ,  H01L29/8122 ,  H01L29/8611 ,  H01L29/872

摘要： The present invention discloses an electronic device using a group III nitride substrate fabricated via the ammonothermal method. By utilizing the high-electron concentration of ammonothermally grown substrates having the dislocation density less than 105 cm−2, combined with a high-purity active layer of Ga1-x-yAlxInyN (0≦x≦1, 0≦y≦1) grown by a vapor phase method, the device can attain high level of breakdown voltage as well as low on-resistance. To realize a good matching between the ammonothermally grown substrate and the high-purity active layer, a transition layer is optionally introduced. The active layer is thicker than a depletion region created by a device structure in the active layer.

摘要翻译： 本发明公开了一种使用通过氨热法制造的III族氮化物衬底的电子器件。 通过利用具有位错密度小于105cm -2的氨基生长的基底的高电子浓度，结合Ga1-x-yAlxInyN（0≤x≤1,0≤y≤1）的高纯度有源层生长 通过气相法，器件可以获得高电平的击穿电压以及低导通电阻。 为了实现氨热生长的基底和高纯度活性层之间的良好匹配，任选地引入过渡层。 有源层比由有源层中的器件结构产生的耗尽区厚。

公开(公告)号：US20150179772A1

公开(公告)日：2015-06-25

申请号：US14489761

申请日：2014-09-18

申请人： Avogy, Inc.

发明人： Richard J. Brown ,  Isik C. Kizilyalli ,  Hui Nie ,  Andrew P. Edwards ,  David P. Bour

IPC分类号： H01L29/66 ,  H01L21/32 ,  H01L29/47 ,  H01L21/02 ,  H01L29/20 ,  H01L29/36

CPC分类号： H01L29/66856 ,  H01L21/0254 ,  H01L21/02647 ,  H01L21/32 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/475 ,  H01L29/8083 ,  H01L29/812 ,  H01L29/8122

摘要： A semiconductor structure includes a III-nitride substrate and a drift region coupled to the III-nitride substrate along a growth direction. The semiconductor substrate also includes a channel region coupled to the drift region. The channel region is defined by a channel sidewall disposed substantially along the growth direction. The semiconductor substrate further includes a gate region disposed laterally with respect to the channel region.

摘要翻译： 半导体结构包括III族氮化物衬底和沿生长方向耦合到III族氮化物衬底的漂移区域。 半导体衬底还包括耦合到漂移区的沟道区。 通道区域由基本沿着生长方向设置的通道侧壁限定。 半导体衬底还包括相对于沟道区域侧向设置的栅极区域。

公开(公告)号：US08981434B2

公开(公告)日：2015-03-17

申请号：US13393002

申请日：2010-06-23

申请人： Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Kazuomi Endo

发明人： Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Kazuomi Endo

IPC分类号： H01L29/76 ,  H01L29/812 ,  H01L29/201 ,  H01L29/78 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/417 ,  H01L29/423

CPC分类号： H01L29/8122 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/7809 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/8128

摘要： Provided is a semiconductor device in which the trade-off between the withstand voltage and the on-resistance is improved and the performance is increased. A semiconductor device comprises a substrate 1, a first n-type semiconductor layer 21′, a second n-type semiconductor layer 23, a p-type semiconductor layer 24, and a third n-type semiconductor layer 25′, wherein the first n-type semiconductor layer 21′, the second n-type semiconductor layer 23, the p-type semiconductor layer 24, and the third n-type semiconductor layer 25′ are laminated at the upper side of the substrate 1 in this order. The drain electrode 13 is in ohmic-contact with the first n-type semiconductor layer 21′ and the source electrode 12 is in ohmic-contact with the third n-type semiconductor layer 25′. A gate electrode 14 is arranged so as to fill an opening portion to be filled that extends from the third n-type semiconductor layer 25′ to the second n-type semiconductor layer 23, and the gate electrode 14 is in contact with the upper surface of the second n-type semiconductor layer 23, the side surfaces of the p-type semiconductor layer 24, and the side surfaces of the third n-type semiconductor layer 25′. The second n-type semiconductor layer 23 has composition that changes from the drain electrode 13 side toward the source electrode 12 side in the direction perpendicular to the plane of the substrate 1 and contains donor impurity.

摘要翻译： 提供一种半导体器件，其中耐压和导通电阻之间的折衷被提高并且性能提高。 半导体器件包括衬底1，第一n型半导体层21'，第二n型半导体层23，p型半导体层24和第三n型半导体层25'，其中第一n型半导体层 型半导体层21'，第二n型半导体层23，p型半导体层24和第三n型半导体层25'依次层叠在基板1的上侧。 漏电极13与第一n型半导体层21'欧姆接触，源电极12与第三n型半导体层25'欧姆接触。 栅电极14被布置成填充从第三n型半导体层25'延伸到第二n型半导体层23的待填充的开口部分，并且栅电极14与上表面 第二n型半导体层23，p型半导体层24的侧表面和第三n型半导体层25'的侧表面。 第二n型半导体层23具有从垂直于基板1的平面的方向从漏电极13侧向源电极12侧变化的成分，并且含有施主杂质。