公开(公告)号：US09034693B2

公开(公告)日：2015-05-19

申请号：US13247890

申请日：2011-09-28

申请人： Il Kwon Shim ,  Kwee Lan Tan ,  Jian Jun Li ,  Dario S. Filoteo, Jr.

发明人： Il Kwon Shim ,  Kwee Lan Tan ,  Jian Jun Li ,  Dario S. Filoteo, Jr.

IPC分类号： H01L21/00 ,  H01L25/065 ,  H01L21/48 ,  H01L23/13 ,  H01L23/498 ,  H01L25/10 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49816 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  Y10S438/928 ,  H01L2924/00012 ,  H01L2924/01031 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacturing an integrated circuit package includes: forming a substrate including: forming a core layer, and forming vias in the core layer; forming a conductive layer having a predetermined thickness on the core layer and having substantially twice the predetermined thickness in the vias; and forming connections between an integrated circuit die and the conductive layer.

摘要翻译： 制造集成电路封装的方法包括：形成衬底，包括：形成芯层，并在芯层中形成通孔; 在芯层上形成具有预定厚度的导电层，并且在通孔中基本上具有预定厚度的两倍; 以及在集成电路管芯和导电层之间形成连接。

公开(公告)号：US07911046B2

公开(公告)日：2011-03-22

申请号：US12391807

申请日：2009-02-24

申请人： Philip Lyndon Cablao ,  Rachel Layda Abinan ,  Dario S. Filoteo, Jr. ,  Allan P. Ilagan

发明人： Philip Lyndon Cablao ,  Rachel Layda Abinan ,  Dario S. Filoteo, Jr. ,  Allan P. Ilagan

IPC分类号： H01L23/00

CPC分类号： H01L24/83 ,  H01L23/13 ,  H01L24/16 ,  H01L24/28 ,  H01L24/31 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L25/0652 ,  H01L25/162 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/4911 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83102 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/92125 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2224/16225 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/16145 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An integrated circuit packaging system is provided including forming an interposer having a coupling slot, securing an upper die on the interposer, mounting the interposer over an integrated circuit, and coupling the integrated circuit to the upper die through the coupling slot.

摘要翻译： 提供了一种集成电路封装系统，包括形成具有耦合槽的插入件，将上模固定在插入器上，将插入件安装在集成电路上，并通过耦合槽将集成电路耦合到上模。

公开(公告)号：US20100144100A1

公开(公告)日：2010-06-10

申请号：US12703450

申请日：2010-02-10

申请人： Emmanuel A. Espiritu ,  Leo A. Merilo ,  Rachel L. Abinan ,  Dario S. Filoteo, JR.

发明人： Emmanuel A. Espiritu ,  Leo A. Merilo ,  Rachel L. Abinan ,  Dario S. Filoteo, JR.

IPC分类号： H01L21/60

CPC分类号： H01L23/3135 ,  H01L23/49551 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

摘要： A semiconductor package includes a leadframe having first and second level downset lead extensions, a quad flat nonleaded package (QFN) attached to the first level downset lead extension, and a flip chip die attached to the second level downset lead extension. Another embodiment of a semiconductor package includes a leadframe having a lead, a first quad flat nonleaded package (QFN) connected to the lead, and a second quad flat nonleaded package invertly connected to a top surface of the first quad flat nonleaded package, wherein the second quad flat nonleaded package is wirebonded to the lead. A third embodiment of a semiconductor package includes a leadframe having a lead with a first level downset lead extension, a quad flat nonleaded package (QFN) connected to the first level downset lead extension, and a first wirebondable die attached to a top or bottom surface of the quad flat nonleaded package.

摘要翻译： 半导体封装包括具有第一和第二级漏极引线延伸部的引线框架，附接到第一级漏极引线延伸部的四边形无铅封装（QFN）以及附接到第二级漏极引线延伸部的倒装芯片管芯。 半导体封装的另一实施例包括具有引线的引线框架，连接到引线的第一四边形扁平无铅封装（QFN）和与第一四边形无铅衬垫封装的顶表面反向连接的第二四边形扁平无铅封装，其中， 第二个四边形扁平无铅封装被引线接合到引线。 半导体封装的第三实施例包括具有引线的引线框架，引线具有第一级漏极引线延伸，连接到第一级漏极引线延伸部的四边形无铅封装（QFN）以及连接到顶表面或底表面的第一可焊接模具 的四边形无铅包装。

公开(公告)号：US07445955B2

公开(公告)日：2008-11-04

申请号：US11160837

申请日：2005-07-12

申请人： Il Kwon Shim ,  Dario S Filoteo, Jr. ,  Tsz Yin Ho ,  Sebastian T. M. Soon

发明人： Il Kwon Shim ,  Dario S Filoteo, Jr. ,  Tsz Yin Ho ,  Sebastian T. M. Soon

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L25/0655 ,  H01L21/50 ,  H01L23/13 ,  H01L23/36 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method for fabricating a multichip module package includes providing a first heat sink positioned for releasing heat from the package and providing a second heat sink positioned proximate the first heat sink. The heat sinks are thermally coupled and electrically isolated to and from one another. A first semiconductor device is attached to the first heat sink in thermal and electrical communication therewith and electrically insulated from the second heat sink. A second semiconductor device is attached to the second heat sink in thermal and electrical communication therewith and electrically insulated from the first heat sink.

摘要翻译： 一种用于制造多芯片组件封装的方法，包括：提供第一散热器，其定位成用于释放来自封装的热量，并提供靠近第一散热器定位的第二散热器。 散热器热耦合并且彼此电隔离。 第一半导体器件被附接到第一散热器，与第一散热器进行热和电通信并与第二散热器电绝缘。 第二半导体器件与第二散热器热连接并与之电气连通，并与第一散热器电绝缘。

公开(公告)号：US20080042265A1

公开(公告)日：2008-02-21

申请号：US11464699

申请日：2006-08-15

申请人： Leo A. Merilo ,  Emmanuel A. Espiritu ,  Dario S. Filoteo ,  Rachel L. Abinan

发明人： Leo A. Merilo ,  Emmanuel A. Espiritu ,  Dario S. Filoteo ,  Rachel L. Abinan

IPC分类号： H01L23/34

CPC分类号： H01L25/162 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15151 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor package includes a ball grid array (BGA) substrate having integrated metal layer circuitry, a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD), the flip chip chip scale module package attached to the ball grid array (BGA) substrate, and an application die attached to the integrated passive device (IPD). A method of manufacturing a semiconductor package includes providing a ball grid array (BGA) substrate having integrated metal layer circuitry, attaching a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD) to the ball grid array (BGA) substrate, and attaching an application die to the integrated passive device (IPD).

摘要翻译： 半导体封装包括具有集成金属层电路的球栅阵列（BGA）衬底，具有第一集成无源器件（IPD）的倒装芯片尺寸模块封装（CSMP），所述倒装芯片级尺模块封装附接到球栅 阵列（BGA）基板和连接到集成无源器件（IPD）的应用裸片）。 制造半导体封装的方法包括提供具有集成金属层电路的球栅阵列（BGA）衬底，将具有第一集成无源器件（IPD）的倒装芯片芯片级模块封装（CSMP）附接到球栅阵列（BGA ）基板，并将应用管芯附接到集成无源器件（IPD）。

公开(公告)号：US09000579B2

公开(公告)日：2015-04-07

申请号：US11694912

申请日：2007-03-30

申请人： Il Kwon Shim ,  Dario S. Filoteo, Jr. ,  Emmanuel Espiritu ,  Rachel Layda Abinan

发明人： Il Kwon Shim ,  Dario S. Filoteo, Jr. ,  Emmanuel Espiritu ,  Rachel Layda Abinan

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L21/44 ,  H01L23/498 ,  H01L23/00

CPC分类号： H01L23/49827 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/85 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/4848 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/85186 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/4554 ,  H01L2224/85399 ,  H01L2224/05599

摘要： An integrated circuit package system includes a substrate having an opening provided therein, forming a conductor in the opening having a closed end at the bottom, attaching an integrated circuit die over the substrate, and connecting a die interconnect to the integrated circuit die and the closed end of the conductor.

摘要翻译： 一种集成电路封装系统，包括其中设置有开口的基板，在该开口中形成在底部具有封闭端的导体，将集成电路裸片安装在基板上，并将芯片互连连接到集成电路管芯和封闭 导体末端。

公开(公告)号：US20120018886A1

公开(公告)日：2012-01-26

申请号：US13247890

申请日：2011-09-28

申请人： Il Kwon Shim ,  Kwee Lan Tan ,  Jian Jun Li ,  Dario S. Filoteo, JR.

发明人： Il Kwon Shim ,  Kwee Lan Tan ,  Jian Jun Li ,  Dario S. Filoteo, JR.

IPC分类号： H01L23/498 ,  H01L21/56

CPC分类号： H01L25/0657 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49816 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  Y10S438/928 ,  H01L2924/00012 ,  H01L2924/01031 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacturing an integrated circuit package includes: forming a substrate including: forming a core layer, and forming vias in the core layer; forming a conductive layer having a predetermined thickness on the core layer and having substantially twice the predetermined thickness in the vias; and forming connections between an integrated circuit die and the conductive layer.

摘要翻译： 制造集成电路封装的方法包括：形成衬底，包括：形成芯层，并在芯层中形成通孔; 在芯层上形成具有预定厚度的导电层，并且在通孔中基本上具有预定厚度的两倍; 以及在集成电路管芯和导电层之间形成连接。

公开(公告)号：US20100140761A1

公开(公告)日：2010-06-10

申请号：US12703461

申请日：2010-02-10

申请人： Emmanuel A. Espiritu ,  Leo A. Merilo ,  Rachel L. Abinan ,  Dario S. Filoteo, JR.

发明人： Emmanuel A. Espiritu ,  Leo A. Merilo ,  Rachel L. Abinan ,  Dario S. Filoteo, JR.

IPC分类号： H01L23/495

CPC分类号： H01L23/3135 ,  H01L23/49551 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

摘要： A semiconductor package includes a leadframe having first and second level downset lead extensions, a quad flat nonleaded package (QFN) attached to the first level downset lead extension, and a flip chip die attached to the second level downset lead extension. Another embodiment of a semiconductor package includes a leadframe having a lead, a first quad flat nonleaded package (QFN) connected to the lead, and a second quad flat nonleaded package invertly connected to a top surface of the first quad flat nonleaded package, wherein the second quad flat nonleaded package is wirebonded to the lead. A third embodiment of a semiconductor package includes a leadframe having a lead with a first level downset lead extension, a quad flat nonleaded package (QFN) connected to the first level downset lead extension, and a first wirebondable die attached to a top or bottom surface of the quad flat nonleaded package.

摘要翻译： 半导体封装包括具有第一和第二级漏极引线延伸部的引线框架，附接到第一级漏极引线延伸部的四边形无铅封装（QFN）以及附接到第二级漏极引线延伸部的倒装芯片管芯。 半导体封装的另一实施例包括具有引线的引线框架，连接到引线的第一四边形扁平无铅封装（QFN）和与第一四边形无铅衬垫封装的顶表面反向连接的第二四边形扁平无铅封装，其中， 第二个四边形扁平无铅封装被引线接合到引线。 半导体封装的第三实施例包括具有引线的引线框架，引线具有第一级漏极引线延伸，连接到第一级漏极引线延伸部的四边形无铅封装（QFN）以及连接到顶表面或底表面的第一可焊接模具 的四边形无铅包装。

公开(公告)号：US20100038771A1

公开(公告)日：2010-02-18

申请号：US12582587

申请日：2009-10-20

申请人： Il Kwon Shim ,  Kwee Lan Tan ,  Jian Jun Li ,  Dario S. Filoteo, JR.

发明人： Il Kwon Shim ,  Kwee Lan Tan ,  Jian Jun Li ,  Dario S. Filoteo, JR.

IPC分类号： H01L23/498 ,  H01L21/56

CPC分类号： H01L25/0657 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49816 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  Y10S438/928 ,  H01L2924/00012 ,  H01L2924/01031 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacturing an integrated circuit package includes: forming a substrate that includes: forming a core layer, forming vias in the core layer, and forming a conductive layer having a predetermined thickness on the core layer and having substantially twice the predetermined thickness in the vias; and forming connections between an integrated circuit die and the conductive layer.

摘要翻译： 制造集成电路封装的方法包括：形成衬底，其包括：形成芯层，在芯层中形成通孔，以及在芯层上形成具有预定厚度的导电层，并且在 过孔 以及在集成电路管芯和导电层之间形成连接。

公开(公告)号：US07659608B2

公开(公告)日：2010-02-09

申请号：US11532387

申请日：2006-09-15

申请人： Philip Lyndon R. Cablao ,  Dario S. Filoteo, Jr. ,  Emmanuel A. Espiritu ,  Leo A. Merilo

发明人： Philip Lyndon R. Cablao ,  Dario S. Filoteo, Jr. ,  Emmanuel A. Espiritu ,  Leo A. Merilo

IPC分类号： H01L23/02 ,  H01L23/495 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L23/3128 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/162 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stacked die semiconductor package includes a first integrated circuit chip, a first circuit tape coupled to the first integrated circuit chip, a second integrated circuit chip coupled to the first circuit tape, and at least one component coupled to the first circuit tape. The at least one component may include one or more passive components, one or more active components, or a combination of passive and active components. The stacked die semiconductor package can also include a second circuit tape coupled to the second integrated circuit chip and a third integrated circuit chip coupled to the second circuit tape. The stacked die semiconductor package can also include an encapsulant.