公开(公告)号：US20150206769A1

公开(公告)日：2015-07-23

申请号：US14160500

申请日：2014-01-21

申请人： Kesvakumar V.C. Muniandy ,  Dominic Koey ,  Navas Khan Oratti Kalandar

发明人： Kesvakumar V.C. Muniandy ,  Dominic Koey ,  Navas Khan Oratti Kalandar

IPC分类号： H01L21/56 ,  H01L23/00 ,  H01L23/495

CPC分类号： H01L21/56 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/49503 ,  H01L23/4952 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L24/96 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48611 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/85 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device includes a semiconductor die having first and second opposing main surfaces and a die bonding pads on the first main surface, and a conductive member having first and second opposing main surfaces that surrounds the die. The die and the conductive member are encapsulated with a first encapsulant and form an expanded die. The expanded die is mounted on a lead frame having conductive leads, and the conductive leads are electrically coupled to the conductive member, which acts as a power bar, and to the die bonding pads. The conductive member also is electrically coupled to at least one of the die bonding pads. The expanded die and portions of the conductive leads are encapsulated with a second encapsulant.

摘要翻译： 半导体器件包括具有第一和第二相对主表面的半导体管芯和在第一主表面上的管芯接合焊盘，以及具有包围管芯的第一和第二相对主表面的导电构件。 模具和导电构件用第一密封剂包封并形成扩展模具。 扩展的管芯安装在具有导电引线的引线框架上，并且导电引线电连接到用作功率棒的导电构件和芯片接合焊盘。 导电构件还电连接到芯片接合焊盘中的至少一个。 扩展的管芯和导电引线的部分用第二密封剂封装。

公开(公告)号：US20160086930A1

公开(公告)日：2016-03-24

申请号：US14494611

申请日：2014-09-24

申请人： Dominic Koey ,  Zhiwei Gong

发明人： Dominic Koey ,  Zhiwei Gong

IPC分类号： H01L25/00 ,  H01L25/18 ,  H01L23/522 ,  H01L21/56 ,  H01L21/768

CPC分类号： H01L25/50 ,  H01L21/486 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/03 ,  H01L25/0652 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24195 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/3511

摘要： Fan-Out Wafer Level Packages (FO-WLPs) include double-sided molded package bodies in which first and second layers of components are embedded in a back-to-back relationship. In one embodiment, the FO-WLP fabrication method includes positioning a first microelectronic component carried by a first temporary substrate in a back-to-back relationship with a second microelectronic component carried by a second temporary substrate. The first and second components are overmolded while positioned in the back-to-back relationship to produce a double-sided molded package body. The first temporary substrate is then removed to expose a first principal surface of the package body at which the first component is exposed, and the second temporary substrate is likewise removed to expose a second, opposing principal surface of the package body at which the second component is exposed.

摘要翻译： 扇出晶圆级封装（FO-WLP）包括双面模制封装体，其中第一和第二层部件以背对背的关系嵌入。 在一个实施例中，FO-WLP制造方法包括以由第二临时衬底承载的第二微电子部件的背对背关系定位由第一临时衬底承载的第一微电子部件。 第一和第二部件被包覆成型，同时以背对背的关系定位，以产生双面模制包装体。 然后去除第一临时衬底以暴露第一部件暴露于封装主体的第一主表面，并且同样去除第二临时衬底以露出封装体的第二相对主表面，在该第二部分处，第二部件 被暴露。

公开(公告)号：US09171786B1

公开(公告)日：2015-10-27

申请号：US14321823

申请日：2014-07-02

申请人： Soon Kang Chan ,  Soo Choong Chee ,  Stanley Job Doraisamy ,  Dominic Koey

发明人： Soon Kang Chan ,  Soo Choong Chee ,  Stanley Job Doraisamy ,  Dominic Koey

IPC分类号： H01L23/48 ,  H01L23/495 ,  H01L23/00 ,  H01L21/306 ,  H01L23/498

CPC分类号： H01L23/49513 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/568 ,  H01L23/498 ,  H01L24/06 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L29/0657 ,  H01L2224/2741 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83104 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/83201 ,  H01L2224/83365 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： An integrated circuit (IC) die has an active side and an inactive side, opposite the active side. A recess is formed within the interior of the inactive side and extends partially through the integrated circuit towards the active side. The IC die is part of a packaged IC device, where the die is attached to a package component such as a lead frame, substrate, or another die, using die attach adhesive that fills the recess, thereby providing a more reliable bond between the IC die and the package component.

摘要翻译： 集成电路（IC）芯片具有与主动侧相对的有源侧和无源侧。 在非活动侧的内部形成凹部，并且部分地穿过集成电路朝向主动侧延伸。 IC芯片是封装的IC器件的一部分，其中芯片使用填充凹部的芯片附着粘合剂附接到诸如引线框架，基板或另一个裸片的封装部件，从而在IC 模具和包装组件。

公开(公告)号：US08980696B2

公开(公告)日：2015-03-17

申请号：US13292103

申请日：2011-11-09

申请人： Dominic Koey Poh Meng ,  Zhiwei Gong ,  Kesvakumar V. C. Muniandy ,  Weng Foong Yap

发明人： Dominic Koey Poh Meng ,  Zhiwei Gong ,  Kesvakumar V. C. Muniandy ,  Weng Foong Yap

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  A01J21/00 ,  A01J25/12 ,  H01L23/498 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L23/24 ,  H01L23/31

CPC分类号： H01L23/49816 ,  H01L21/561 ,  H01L21/568 ,  H01L23/24 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/97 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/12042 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/00

摘要： A method of packaging a semiconductor die includes the use of an embedded ground plane or drop-in embedded unit. The embedded unit is a single, stand-alone unit with at least one cavity. The embedded unit is placed on and within an encapsulation area of a process mounting surface. The embedded unit may have different sizes and shapes and a number of different cavities that can be placed in a predetermined position on a substrate, panel or tape during processing of semiconductor dies that are embedded into redistributed chip package (RCP) or wafer level package (WFL) panels. The embedded unit provides the functionality and design flexibility to run a number of embedded units and semiconductor dies or components having different sizes and dimensions in a single processing panel or batch and reduces die drift, movement or skew during encapsulation and post-encapsulation cure.

摘要翻译： 封装半导体管芯的方法包括使用嵌入式接地层或嵌入式嵌入式单元。 嵌入式单元是具有至少一个空腔的单个独立单元。 嵌入式单元被放置在过程安装表面的封装区域内和之内。 嵌入式单元可以具有不同的尺寸和形状以及在处理半导体管芯期间可以放置在基板，面板或带上的预定位置的多个不同的空腔，该半导体管芯嵌入到再分布芯片封装（RCP）或晶片级封装 WFL）面板。 嵌入式单元提供功能和设计灵活性，可以在单个处理面板或批次中运行多个嵌入式单元和半导体管芯或具有不同尺寸和尺寸的部件，并减少封装和封装后固化期间的管芯漂移，移动或歪斜。

公开(公告)号：US08765527B1

公开(公告)日：2014-07-01

申请号：US13917639

申请日：2013-06-13

申请人： Dominic Koey

发明人： Dominic Koey

IPC分类号： H01L21/44 ,  H01L21/82

CPC分类号： H01L21/561 ,  H01L21/568 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00

摘要： A method of assembling Redistributed Chip Package (RCP) semiconductor devices. An active die structure is encapsulated in a molding compound with internal electrical contacts of the active die structure positioned at an active face of an encapsulation layer. A dummy die structure is positioned at a back face of the encapsulation layer. A redistribution layer is formed at an active face of the encapsulation layer. The redistribution layer includes a layer of insulating material and redistribution electrical interconnections. The insulating material is built up with grooves along saw streets. External electrical contacts exposed at a surface of the redistribution layer are connected with the redistribution electrical interconnections. The dummy die structure is removed and then the semiconductor devices are singulated.

摘要翻译： 一种组装重分布芯片封装（RCP）半导体器件的方法。 活性模具结构被封装在模制化合物中，活性模具结构的内部电触点位于封装层的有效面上。 虚设管芯结构位于封装层的背面。 在封装层的有源面上形成再分配层。 再分布层包括绝缘材料层和再分布电互连。 绝缘材料沿锯街道形成沟槽。 暴露在再分布层的表面的外部电触点与再分布电互连相连接。 去除虚设管芯结构，然后将半导体器件分割。

公开(公告)号：US20130113091A1

公开(公告)日：2013-05-09

申请号：US13292103

申请日：2011-11-09

申请人： Dominic Koey Poh Meng ,  Zhiwei Gong ,  Kesvakumar V.C. Muniandy ,  Weng Foong Yap

发明人： Dominic Koey Poh Meng ,  Zhiwei Gong ,  Kesvakumar V.C. Muniandy ,  Weng Foong Yap

IPC分类号： H01L23/28 ,  B29C33/12 ,  H01L21/56

CPC分类号： H01L23/49816 ,  H01L21/561 ,  H01L21/568 ,  H01L23/24 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/97 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/12042 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/00

摘要： A method of packaging a semiconductor die includes the use of an embedded ground plane or drop-in embedded unit. The embedded unit is a single, stand-alone unit with at least one cavity. The embedded unit is placed on and within an encapsulation area of a process mounting surface. The embedded unit may have different sizes and shapes and a number of different cavities that can be placed in a predetermined position on a substrate, panel or tape during processing of semiconductor dies that are embedded into redistributed chip package (RCP) or wafer level package (WFL) panels. The embedded unit provides the functionality and design flexibility to run a number of embedded units and semiconductor dies or components having different sizes and dimensions in a single processing panel or batch and reduces die drift, movement or skew during encapsulation and post-encapsulation cure.

摘要翻译： 封装半导体管芯的方法包括使用嵌入式接地层或嵌入式嵌入式单元。 嵌入式单元是具有至少一个空腔的单个独立单元。 嵌入式单元被放置在过程安装表面的封装区域内和之内。 嵌入式单元可以具有不同的尺寸和形状以及在处理半导体管芯期间可以放置在基板，面板或带上的预定位置中的多个不同的空腔，该半导体管芯嵌入到再分布芯片封装（RCP）或晶片级封装 WFL）面板。 嵌入式单元提供功能和设计灵活性，可以在单个处理面板或批次中运行多个嵌入式单元和半导体管芯或具有不同尺寸和尺寸的部件，并减少封装和封装后固化期间的裸片漂移，移动或偏斜。