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公开(公告)号：US20150206769A1
公开(公告)日：2015-07-23
申请号：US14160500
申请日：2014-01-21
IPC分类号： H01L21/56 , H01L23/00 , H01L23/495
CPC分类号： H01L21/56 , H01L21/568 , H01L23/3107 , H01L23/3135 , H01L23/49503 , H01L23/4952 , H01L24/45 , H01L24/48 , H01L24/85 , H01L24/96 , H01L2224/04042 , H01L2224/04105 , H01L2224/05611 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48611 , H01L2224/48644 , H01L2224/48647 , H01L2224/48655 , H01L2224/48664 , H01L2224/85 , H01L2924/181 , H01L2924/19107 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device includes a semiconductor die having first and second opposing main surfaces and a die bonding pads on the first main surface, and a conductive member having first and second opposing main surfaces that surrounds the die. The die and the conductive member are encapsulated with a first encapsulant and form an expanded die. The expanded die is mounted on a lead frame having conductive leads, and the conductive leads are electrically coupled to the conductive member, which acts as a power bar, and to the die bonding pads. The conductive member also is electrically coupled to at least one of the die bonding pads. The expanded die and portions of the conductive leads are encapsulated with a second encapsulant.
摘要翻译： 半导体器件包括具有第一和第二相对主表面的半导体管芯和在第一主表面上的管芯接合焊盘，以及具有包围管芯的第一和第二相对主表面的导电构件。 模具和导电构件用第一密封剂包封并形成扩展模具。 扩展的管芯安装在具有导电引线的引线框架上，并且导电引线电连接到用作功率棒的导电构件和芯片接合焊盘。 导电构件还电连接到芯片接合焊盘中的至少一个。 扩展的管芯和导电引线的部分用第二密封剂封装。
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公开(公告)号：US20130344656A1
公开(公告)日：2013-12-26
申请号：US13530117
申请日：2012-06-22
IPC分类号： H01L21/78
CPC分类号： H01L21/561 , H01L21/486 , H01L21/568 , H01L23/142 , H01L23/3128 , H01L23/3735 , H01L23/5389 , H01L24/19 , H01L24/96 , H01L24/97 , H01L25/105 , H01L2224/12105 , H01L2224/16225 , H01L2224/73267 , H01L2224/9222 , H01L2224/97 , H01L2225/1035 , H01L2225/1058 , H01L2924/12042 , H01L2924/181 , H01L2224/83 , H01L2924/00
摘要： A method of assembling semiconductor devices includes providing a structure that includes an array of conductive frame members beside an array of apertures and an array of conductive vias that are exposed at a first face and extend towards a second face. An array of semiconductor dies is positioned in the array of apertures with their active faces positioned in the first face of the structure. The assembly is encapsulated from the second face of the structure and a redistribution layer is formed on the first face of the structure and the active faces of the die. Material is removed from the back face of the encapsulated array to expose the vias at the back face for connection through a further redistribution layer formed on the back face to electronic components stacked vertically on the further redistribution layer.
摘要翻译： 一种组装半导体器件的方法包括提供一种结构，其包括除了孔阵列之外的导电框架构件的阵列和在第一面处暴露并朝向第二面延伸的导电通孔阵列。 一组半导体管芯位于孔阵列中，其主动面位于结构的第一面。 组件从结构的第二面被封装，并且在结构的第一面和模具的有效面上形成再分布层。 从封装阵列的背面去除材料以暴露在背面的通孔，用于通过形成在背面上的另一重新分配层与垂直堆叠在再分布层上的电子部件连接。
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公开(公告)号：US20130341796A1
公开(公告)日：2013-12-26
申请号：US13530118
申请日：2012-06-22
IPC分类号： H01L23/528 , H01L21/78
CPC分类号： H01L23/49827 , H01L21/563 , H01L23/3128 , H01L23/49816 , H01L2224/16225 , H01L2924/15311
摘要： A semiconductor device has external, exposed electrical contacts at an device active face and a semiconductor die, which has internal, electrical contacts at a die active face. The exposed contacts are offset from the internal contacts laterally of the device active face. A redistribution layer includes a layer of insulating material and redistribution interconnectors within the insulating material, the interconnectors connecting with the exposed contacts. A set of conductors connect the internal contacts and the interconnectors. The conductors have oblong, tear drop shaped cross-sections extending laterally of the die active face beyond the respective internal contacts, and contact the interconnectors at positions spaced further apart than the internal contacts. The redistribution layer may be prefabricated using less costly manufacturing techniques such as lamination.
摘要翻译： 半导体器件在器件主动面和半导体管芯处具有外部暴露的电触头，半导体管芯在管芯主动面处具有内部电接触。 暴露的触点从设备主动面侧面的内部触点偏移。 再分配层包括绝缘材料层和绝缘材料内的再分配互连器，该连接器与暴露的触点连接。 一组导体连接内部触点和互连器。 导体具有长圆形的泪滴形横截面，其横向延伸到模具主动面的外侧，超过相应的内部触点，并且在相互间隔开的位置处与互连器接触。 可以使用较便宜的制造技术（例如层压）来预制再分布层。
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公开(公告)号：US20150115420A1
公开(公告)日：2015-04-30
申请号：US14069358
申请日：2013-10-31
IPC分类号： H01L23/495 , H01L21/56 , H01L21/48
CPC分类号： H01L21/561 , G01L19/0084 , H01L21/4825 , H01L21/486 , H01L21/568 , H01L23/3128 , H01L23/5384 , H01L23/5389 , H01L24/19 , H01L24/96 , H01L25/0655 , H01L25/18 , H01L2224/04105 , H01L2224/12105 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/00012
摘要： A semiconductor sensor die grid array package includes a semiconductor die having an active surface and an opposite backside surface. The active surface has external die connection pads. Conductive runners respectively connect the die connection pads to external connection mounts of the package. An encapsulant covers the semiconductor die. The encapsulant has a base surface proximal to the conductive runners and a stacking surface opposite the base surface. A sensor die is supported on the stacking surface. The sensor die has an active surface and an opposite backside surface that faces the stacking surface, and the sensor active surface has sensor connection pads. Conductive vias engage with the conductive runners and also are wire bonded to one of the sensor connection pads.
摘要翻译： 半导体传感器管芯阵列封装包括具有有源表面和相对的背面的半导体管芯。 有源表面具有外部管芯连接焊盘。 导电滑块将模具连接垫分别连接到包装的外部连接支架上。 密封剂覆盖半导体管芯。 密封剂具有靠近导电流道的基部表面和与基底表面相对的堆叠表面。 传感器模具被支撑在堆叠表面上。 传感器芯片具有面向堆叠表面的有源表面和相对的背面，并且传感器有源表面具有传感器连接焊盘。 导电通孔与导电流道接合，并且还被导线接合到传感器连接垫之一。
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公开(公告)号：US20150187728A1
公开(公告)日：2015-07-02
申请号：US14141465
申请日：2013-12-27
IPC分类号： H01L23/00
CPC分类号： H01L24/03 , H01L23/5286 , H01L23/5328 , H01L24/05 , H01L24/06 , H01L24/09 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/04042 , H01L2224/05553 , H01L2224/06135 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2224/92247 , H01L2924/00014 , H01L2924/14 , H01L2924/00012 , H01L2224/45099 , H01L2924/00 , H01L2224/05599 , H01L2224/45015 , H01L2924/207
摘要： In a packaged semiconductor device, a die is mounted on a substrate having power connection pads. An exterior (e.g., top) surface of the die has power bond pads and distributed power feed pads. Bond wires electrically connect the power connection pads of the substrate to the power bond pads of the die, and exterior conductive structures electrically connect the power bond pads of the die to the distributed power feed pads of the die. The exterior conductive structures are printed or pasted onto the exterior die surface. Using exterior conductive structures instead of interior conductive traces (in the die) reduces resistive power losses and frees up more room for routing signals within the interior die layers.
摘要翻译： 在封装半导体器件中，裸片安装在具有电源连接焊盘的基板上。 管芯的外部（例如顶部）表面具有电力接合焊盘和分布式馈电焊盘。 接合线将衬底的电源连接焊盘电连接到管芯的电源接合焊盘，并且外部导电结构将管芯的功率接合焊盘电连接到管芯的分布式馈电焊盘。 外部导电结构被印刷或粘贴到外部模具表面上。 使用外部导电结构代替内部导电迹线（在管芯中）可以降低电阻功率损耗，并释放更多的内部管芯层内路由信号的空间。
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公开(公告)号：US20140302641A1
公开(公告)日：2014-10-09
申请号：US14292938
申请日：2014-06-01
IPC分类号： H01L23/00 , H01L23/367 , H01L21/56 , H01L21/78
CPC分类号： H01L23/562 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L21/78 , H01L23/16 , H01L23/3128 , H01L23/367 , H01L23/42 , H01L23/49805 , H01L23/49816 , H01L23/5389 , H01L23/585 , H01L24/19 , H01L2221/68327 , H01L2221/6834 , H01L2224/16225 , H01L2924/15311 , H01L2924/15787 , H01L2924/181 , H01L2924/00
摘要： A stiffened semiconductor die package has a semiconductor die including an integrated circuit. The die has an active side with die bonding pads and an opposite inactive side. A conductive frame that acts as a ground plane surrounds all edges of the die and a mold compound covers the conductive frame and the edges of the die. A thermally conductive sheet is attached to the inactive side of the die. A dielectric support structure with external connector pads with solder deposits is attached to the active side of the die. The external connector pads are selectively electrically coupled to the die bonding pads.
摘要翻译： 加强半导体管芯封装具有包括集成电路的半导体管芯。 模具具有活性侧，具有芯片焊盘和相反的无效侧。 用作接地平面的导电框架围绕模具的所有边缘，并且模具化合物覆盖导电框架和模具的边缘。 导热片附接到模具的不活动侧。 具有焊料沉积物的外部连接器焊盘的电介质支撑结构附接到管芯的有源侧。 外部连接器焊盘选择性地电连接到管芯接合焊盘。
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公开(公告)号：US20160056094A1
公开(公告)日：2016-02-25
申请号：US14463651
申请日：2014-08-19
IPC分类号： H01L23/495 , H01L21/56 , H01L21/48
CPC分类号： H01L23/36 , H01L21/4846 , H01L21/568 , H01L23/49816 , H01L23/49833 , H01L23/49838 , H01L23/49894 , H01L23/5389 , H01L24/19 , H01L24/96 , H01L24/97 , H01L2224/04105 , H01L2224/12105 , H01L2224/24155 , H01L2224/32245 , H01L2224/73267 , H01L2224/9222 , H01L2924/18162
摘要： A semiconductor package includes a substrate, a die mounted on a first side of the substrate, an array of solder balls mounted on a second, opposite side of the substrate, and a signal-routing structure mounted on the first side of the substrate and adjacent to the die. The substrate and the signal-routing structure provide electrical connections between die pads on the die and some of the solder balls.
摘要翻译： 半导体封装包括衬底，安装在衬底的第一侧上的管芯，安装在衬底的第二相对侧上的焊球的阵列，以及安装在衬底的第一侧上的相邻的信号布线结构 去死 基板和信号布线结构提供了管芯上的管芯焊盘和一些焊球之间的电连接。
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8.发明申请公开(公告)号：US20140231977A1
公开(公告)日：2014-08-21
申请号：US13773578
申请日：2013-02-21
IPC分类号： H01L23/498 , H01L21/78 , H01L23/495 , H01L21/56
CPC分类号： H01L21/78 , H01L21/561 , H01L23/3121 , H01L24/97 , H01L2224/16145 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2924/181 , H01L2924/00014 , H01L2924/00
摘要： A method of forming a semiconductor package includes providing a support and a first semiconductor die, each having first and second main surfaces. The second main surface of the first die is disposed on the first main surface of the support. Stud bumps are formed on the first main surface of the first die. A surface of a second semiconductor die is bonded to the stud bumps. The first main surface of the first die is wire bonded to the first main surface of the support. The first and second dies, the stud bumps, the bond wire, and at least a portion of the first main surface of the support are encapsulated with a mold compound.
摘要翻译： 形成半导体封装的方法包括提供支撑件和第一半导体管芯，每个具有第一和第二主表面。 第一管芯的第二主表面设置在支撑件的第一主表面上。 在第一模具的第一主表面上形成螺柱凸块。 第二半导体管芯的表面被接合到螺柱凸块。 第一模具的第一主表面被引线接合到支撑件的第一主表面。 第一和第二模具，柱形凸起，接合线以及支撑体的第一主表面的至少一部分用模具化合物包封。
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公开(公告)号：US09190355B2
公开(公告)日：2015-11-17
申请号：US14255957
申请日：2014-04-18
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/498 , H01L23/00
CPC分类号： H01L23/49811 , H01L23/3121 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L24/16 , H01L24/32 , H01L24/33 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/85 , H01L24/90 , H01L2224/05599 , H01L2224/16227 , H01L2224/26165 , H01L2224/32225 , H01L2224/48106 , H01L2224/48227 , H01L2224/48228 , H01L2224/49171 , H01L2224/49175 , H01L2224/73204 , H01L2224/73265 , H01L2224/83385 , H01L2224/8385 , H01L2224/85444 , H01L2924/00014 , H01L2924/01029 , H01L2924/14 , H01L2924/15311 , H01L2924/15312 , H01L2924/15313 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/16225 , H01L2224/45099
摘要： A sub-assembly for a packaged integrated circuit (IC) device has a planar substrate. The substrate's top side has multiple sets electrically connected bond posts arranged in corresponding nested contour zones. Each contour zone includes a different bond post of each bond-post set. The bottom side has a different set of pad connectors electrically connected to the each top-side bond-post set. The sub-assembly can be used for different IC packages having IC dies of different sizes, with different contours of bond posts available for electrical connection depending on the size of the IC die.
摘要翻译： 用于封装集成电路（IC）器件的子组件具有平面衬底。 基板的顶侧具有布置在相应嵌套轮廓区域中的多组电连接的接合柱。 每个轮廓区域包括每个债券 - 债券集合的不同债券债券。 底侧具有电连接到每个顶侧粘结柱组的不同组的焊盘连接器。 子组件可用于具有不同尺寸的IC芯片的不同IC封装，根据IC芯片的尺寸，具有可用于电连接的不同等级的焊接柱。
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公开(公告)号：US09159682B2
公开(公告)日：2015-10-13
申请号：US14020841
申请日：2013-09-08
IPC分类号： H01L21/44 , H01L23/00 , H01L23/498
CPC分类号： H01L24/11 , H01L23/49811 , H01L23/49816 , H01L23/49822 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/92 , H01L2224/03424 , H01L2224/03464 , H01L2224/0401 , H01L2224/05155 , H01L2224/05644 , H01L2224/10175 , H01L2224/11462 , H01L2224/1147 , H01L2224/11474 , H01L2224/1148 , H01L2224/11849 , H01L2224/13147 , H01L2224/14131 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/81192 , H01L2224/81203 , H01L2224/8121 , H01L2224/81815 , H01L2224/83102 , H01L2224/9211 , H01L2224/92125 , H01L2924/01029 , H01L2924/15311 , H01L2924/181 , H01L2924/381 , H01L2924/3841 , H05K3/4007 , H05K2201/0367 , H01L2924/00014 , H01L2924/00012 , H01L2224/81 , H01L2224/83 , H01L2924/00
摘要： Electrically conductive pillars with a solder cap are formed on a substrate with an electroplating process. A flip-chip die having solder wettable pads is attached to the substrate with the conductive pillars contacting the solder wettable pads.
摘要翻译： 具有焊接帽的导电柱形成在具有电镀工艺的基板上。 具有焊料可湿性焊盘的倒装芯片裸片被附着到基板上，导电柱接触可焊接的可湿性焊盘。
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