摘要:
Provided is a method of preparing an activated mineral solution, which includes steps of pulverizing granite and/or vermiculite into a powder by grinding, subjecting the powder to an electrolysis treatment, dissolving the powder in an aqueous ammonia solution and an acidic solution to prepare a mixed solution, emitting ultrasonic waves on the mixed solution, introducing microorganisms onto the mixed solution, and neutralizing the mixed solution, in which the mineral is selected from the group consisting of Fe, Mg, Al, Ti, K, Ca, Mn, Nb, P, Na, Zn, V, Cr, Ni, Si, B, Cu, Li, Ga, Co, Sr, In, Rb, Sb, Ta, Y, and combinations thereof.
摘要:
A method of programming a non-volatile memory includes executing at least two program loops on memory cells in a selected word line, generating a fail bit trend based on a result of executing each of the at least two program loops, predicting a plurality of program loops comprising an N program loop to be executed last on the memory cells, based on the generated fail bit trend, and changing, based on a result of predicting the plurality of program loops, a level of an N program voltage provided to the memory cells when the N program loop is executed.
摘要:
A method of preparing an ionized calcium oxide powder is provided, including steps of washing and drying shellfish, pulverizing the shellfish into a powder, subjecting the powder to a heat treatment, subjecting the powder to an electrolysis treatment, and subjecting the powder to an ultrasonic treatment.
摘要:
A memory device, comprising: a memory cell array including a plurality of NAND strings, each NAND string including a plurality of memory cells respectively connected to a plurality of word lines vertically stacked on a substrate; and a control logic configured to generate a pre-programming control signal for memory cells of a first NAND string of the NAND strings such that, before erasing the memory cells of the first NAND string, pre-programming voltages applied to the word lines coupled to the corresponding memory cells of the first NAND string vary based on an operating characteristic of the corresponding memory cells.
摘要:
A method of fabricating semiconductor devices may include forming a mold structure on a lower layer, the mold structure including an etch stop layer doped at a first impurity concentration, a lower mold layer doped at a second impurity concentration, and an undoped upper mold layer. The method may include forming a trench exposing the lower layer in the mold structure using dry etching, extending a width of the trench in the etch stop layer using wet etching, and forming a first conductive pattern in the extended width trench, wherein an etch rate of the etch stop layer with respect to the dry etching may be smaller than an etch rate of the lower mold layer with respect to the dry etching, and an etch rate of the etch stop layer with respect to the wet etching may be proportional to the first impurity concentration.
摘要:
A method of fabricating semiconductor devices may include forming a mold structure on a lower layer, the mold structure including an etch stop layer doped at a first impurity concentration, a lower mold layer doped at a second impurity concentration, and an undoped upper mold layer. The method may include forming a trench exposing the lower layer in the mold structure using dry etching, extending a width of the trench in the etch stop layer using wet etching, and forming a first conductive pattern in the extended width trench, wherein an etch rate of the etch stop layer with respect to the dry etching may be smaller than an etch rate of the lower mold layer with respect to the dry etching, and an etch rate of the etch stop layer with respect to the wet etching may be proportional to the first impurity concentration.
摘要:
A recessed channel array transistor may include a substrate, a gate oxide layer, a gate electrode and source/drain regions. The substrate may have an active region and an isolation region. A recess may be formed in the active region. The gate oxide layer may be formed on the recess and the substrate. The gate oxide layer may include a first portion on an intersection between a side end of the recess and a sidewall of the active region and a second portion on a side surface of the recess. The first portion may include a thickness greater than about 70% of a thickness of the second portion. The gate electrode may be formed on the gate oxide layer. The source/drain regions may be formed in the substrate. Thus, the recessed channel array transistor may have a decreased leakage current and an increased on-current.
摘要:
An apparatus and method for matching impedance of an antenna by using Standing Wave Ratio (SWR) information is provided. While the impedance of the impedance matching unit is controlled, a region of a Smith chart in which initial total impedance of the impedance matching unit and the antenna is located by using an SWR calculated by an SWR operation unit, and the impedance of the impedance matching unit is controlled according to the determined region, thus correctly matching the impedance of the antenna.
摘要:
A terminal apparatus includes an interface to detect a touch input, to detect a touch region corresponding to the touch input, and to identify an object that is overlapped by the touch input by at least a reference percentage in the touch region as a first object; a processing unit to generate a second object based on the first object, and to display the second object in an untouched region; and a control unit to execute an operation corresponding to the second object. A method for executing an operation according to a touch input includes detecting a touch input and a corresponding touch region; identifying an object overlapped by at least a reference percentage in the touch region as a first object; generating a second object based on the first object; displaying the second object in an untouched region; and executing an operation corresponding to the second object.
摘要:
A semiconductor device includes a via structure having a top surface with a planar portion and a protrusion portion that is surrounded by the planar portion, and includes a conductive structure including a plurality of conductive lines contacting at least a part of the top surface of the via structure.