公开(公告)号：US09484219B2

公开(公告)日：2016-11-01

申请号：US14826845

申请日：2015-08-14

申请人： Young-Geun Park ,  Wook-Yeol Yi ,  Sang-Yeol Kang ,  Dong-Chan Kim ,  Chang-Mu An ,  Bong-Hyun Kim ,  Han-Jin Lim

发明人： Young-Geun Park ,  Wook-Yeol Yi ,  Sang-Yeol Kang ,  Dong-Chan Kim ,  Chang-Mu An ,  Bong-Hyun Kim ,  Han-Jin Lim

IPC分类号： H01L21/8242 ,  H01L21/311 ,  H01L27/108

CPC分类号： H01L21/31144 ,  H01L21/31111 ,  H01L21/31116 ,  H01L27/10852 ,  H01L27/10855

摘要： A method of fabricating semiconductor devices may include forming a mold structure on a lower layer, the mold structure including an etch stop layer doped at a first impurity concentration, a lower mold layer doped at a second impurity concentration, and an undoped upper mold layer. The method may include forming a trench exposing the lower layer in the mold structure using dry etching, extending a width of the trench in the etch stop layer using wet etching, and forming a first conductive pattern in the extended width trench, wherein an etch rate of the etch stop layer with respect to the dry etching may be smaller than an etch rate of the lower mold layer with respect to the dry etching, and an etch rate of the etch stop layer with respect to the wet etching may be proportional to the first impurity concentration.

摘要翻译： 制造半导体器件的方法可以包括在下层上形成模具结构，所述模具结构包括以第一杂质浓度掺杂的蚀刻停止层，以第二杂质浓度掺杂的下模层和未掺杂的上模层。 该方法可以包括使用干蚀刻形成在模具结构中暴露下层的沟槽，使用湿蚀刻在蚀刻停止层中延伸沟槽的宽度，以及在扩展宽度沟槽中形成第一导电图案，其中蚀刻速率 相对于干蚀刻的蚀刻停止层的蚀刻速度可以小于相对于干蚀刻的下模层的蚀刻速率，并且蚀刻停止层相对于湿蚀刻的蚀刻速率可以与 第一杂质浓度。

公开(公告)号：US20160064386A1

公开(公告)日：2016-03-03

申请号：US14826845

申请日：2015-08-14

申请人： Young-Geun PARK ,  Wook-Yeol YI ,  Sang-Yeol KANG ,  Dong-Chan KIM ,  Chang-Mu AN ,  Bong-Hyun KIM ,  Han-Jin LIM

发明人： Young-Geun PARK ,  Wook-Yeol YI ,  Sang-Yeol KANG ,  Dong-Chan KIM ,  Chang-Mu AN ,  Bong-Hyun KIM ,  Han-Jin LIM

IPC分类号： H01L27/108 ,  H01L21/311

CPC分类号： H01L21/31144 ,  H01L21/31111 ,  H01L21/31116 ,  H01L27/10852 ,  H01L27/10855

摘要： A method of fabricating semiconductor devices may include forming a mold structure on a lower layer, the mold structure including an etch stop layer doped at a first impurity concentration, a lower mold layer doped at a second impurity concentration, and an undoped upper mold layer. The method may include forming a trench exposing the lower layer in the mold structure using dry etching, extending a width of the trench in the etch stop layer using wet etching, and forming a first conductive pattern in the extended width trench, wherein an etch rate of the etch stop layer with respect to the dry etching may be smaller than an etch rate of the lower mold layer with respect to the dry etching, and an etch rate of the etch stop layer with respect to the wet etching may be proportional to the first impurity concentration.

摘要翻译： 制造半导体器件的方法可以包括在下层上形成模具结构，所述模具结构包括以第一杂质浓度掺杂的蚀刻停止层，以第二杂质浓度掺杂的下模层和未掺杂的上模层。 该方法可以包括使用干蚀刻形成在模具结构中暴露下层的沟槽，使用湿蚀刻在蚀刻停止层中延伸沟槽的宽度，以及在扩展宽度沟槽中形成第一导电图案，其中蚀刻速率 相对于干蚀刻的蚀刻停止层的蚀刻速度可以小于相对于干蚀刻的下模层的蚀刻速率，并且蚀刻停止层相对于湿蚀刻的蚀刻速率可以与 第一杂质浓度。

公开(公告)号：US08859383B2

公开(公告)日：2014-10-14

申请号：US13424825

申请日：2012-03-20

申请人： Youn-soo Kim ,  Jae-hyoung Choi ,  Kyu-ho Cho ,  Wan-don Kim ,  Jae-soon Lim ,  Sang-yeol Kang

发明人： Youn-soo Kim ,  Jae-hyoung Choi ,  Kyu-ho Cho ,  Wan-don Kim ,  Jae-soon Lim ,  Sang-yeol Kang

IPC分类号： H01L21/20 ,  H01L49/02 ,  H01L21/02 ,  H01L21/316 ,  H01L21/318 ,  H01L27/108

CPC分类号： H01L28/56 ,  H01L21/02189 ,  H01L21/022 ,  H01L21/02244 ,  H01L21/02247 ,  H01L21/31683 ,  H01L21/318 ,  H01L27/1085 ,  H01L28/40 ,  H01L28/75

摘要： A semiconductor device having a dielectric layer with improved electrical characteristics and associated methods, the semiconductor device including a lower metal layer, a dielectric layer, and an upper metal layer sequentially disposed on a semiconductor substrate and an insertion layer disposed between the dielectric layer and at least one of the lower metal layer and the upper metal layer, wherein the dielectric layer includes a metal oxide film and the insertion layer includes a metallic material film.

摘要翻译： 一种半导体器件，具有具有改善的电特性和相关方法的电介质层，所述半导体器件包括顺序地设置在半导体衬底上的下金属层，电介质层和上金属层，以及设置在电介质层之间的插入层 下金属层和上金属层中的至少一个，其中电介质层包括金属氧化物膜，并且插入层包括金属材料膜。

公开(公告)号：US20130244445A1

公开(公告)日：2013-09-19

申请号：US13775595

申请日：2013-02-25

申请人： Min-Young Park ,  Youn-Soo Kim ,  Sang-Yeol Kang ,  Cha-Young Yoo ,  Jae-Soon Lim ,  Jae-Hyoung Choi

发明人： Min-Young Park ,  Youn-Soo Kim ,  Sang-Yeol Kang ,  Cha-Young Yoo ,  Jae-Soon Lim ,  Jae-Hyoung Choi

IPC分类号： H01L21/02

CPC分类号： H01L21/02104 ,  C23C16/045 ,  C23C16/405 ,  C23C16/45527 ,  H01L21/28282 ,  H01L28/40

摘要： Methods of fabricating a semiconductor device include forming a deposited film on a semiconductor substrate in a process chamber by repeatedly forming unit layers on the semiconductor substrate. The unit layer is formed by forming a preliminary unit layer on the semiconductor substrate by supplying a process material including a precursor material and film-control material into the process chamber, purging the process chamber, forming a unit layer from the preliminary unit layer, and again purging the process chamber. The precursor material includes a central atom and a ligand bonded to the central atom, and the film-control material includes a hydride of the ligand.

摘要翻译： 制造半导体器件的方法包括通过在半导体衬底上重复形成单位层，在处理室中的半导体衬底上形成沉积膜。 单元层通过在半导体基板上形成预备单元层而形成，该方法是将包括前体材料和薄膜控制材料的处理材料供应到处理室中，从处理室中清除处理室，从预备单元层形成单位层，以及 再次清洗处理室。 前体材料包括中心原子和与中心原子键合的配体，膜控制材料包括配体的氢化物。

公开(公告)号：US20120276721A1

公开(公告)日：2012-11-01

申请号：US13459136

申请日：2012-04-28

申请人： Suk-jin Chung ,  Jong-cheol Lee ,  Youn-soo Kim ,  Cha-young Yoo ,  Sang-yeol Kang

发明人： Suk-jin Chung ,  Jong-cheol Lee ,  Youn-soo Kim ,  Cha-young Yoo ,  Sang-yeol Kang

IPC分类号： H01L21/20

CPC分类号： H01L21/02178 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/02312 ,  H01L21/28282 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/1157 ,  H01L27/11582 ,  H01L28/91 ,  H01L29/66795 ,  H01L29/7926

摘要： A method of forming an oxide layer. The method includes: forming a layer of reaction-inhibiting functional groups on a surface of a substrate; forming a layer of precursors of a metal or a semiconductor on the layer of the reaction-inhibiting functional groups; and oxidizing the precursors of the metal or the semiconductor in order to obtain a layer of a metal oxide or a semiconductor oxide. According to the method, an oxide layer having a high thickness uniformity may be formed and a semiconductor device having excellent electrical characteristics may be manufactured.

摘要翻译： 一种形成氧化物层的方法。 该方法包括：在基板的表面上形成反应抑制性官能团层; 在反应抑制官能团的层上形成金属或半导体的前体层; 以及氧化金属或半导体的前体以获得金属氧化物或半导体氧化物的层。 根据该方法，可以形成具有高厚度均匀性的氧化物层，并且可以制造具有优异电特性的半导体器件。

公开(公告)号：US08110473B2

公开(公告)日：2012-02-07

申请号：US12635013

申请日：2009-12-10

申请人： Sang-yeol Kang ,  Jong-cheol Lee ,  Ki-vin Lim ,  Hoon-sang Choi ,  Eun-ae Chung

发明人： Sang-yeol Kang ,  Jong-cheol Lee ,  Ki-vin Lim ,  Hoon-sang Choi ,  Eun-ae Chung

IPC分类号： H01L21/02

CPC分类号： H01L28/40 ,  H01L27/10852

摘要： A semiconductor device including a multilayer dielectric film and a method for fabricating the semiconductor device are disclosed. The multilayer dielectric film includes a type-one dielectric film having a tetragonal crystalline structure, wherein the type-one dielectric film comprises a first substance. The multilayer dielectric film also comprises a type-two dielectric film also having a tetragonal crystalline structure, wherein the type-two dielectric film comprises a second substance different from the first substance and a dielectric constant of the type-two dielectric film is greater than a dielectric constant of the type-one dielectric film.

摘要翻译： 公开了一种包括多层介质膜的半导体器件和用于制造半导体器件的方法。 所述多层电介质膜包括具有四方晶系结构的一型电介质膜，其中，所述一型电介质膜包含第一物质。 所述多层绝缘膜还包括也具有四方晶系结构的二型电介质膜，其中所述二型电介质膜包括与所述第一物质不同的第二物质，并且所述二型电介质膜的介电常数大于 介电常数介电常数为1。

公开(公告)号：US20110102968A1

公开(公告)日：2011-05-05

申请号：US12838296

申请日：2010-07-16

申请人： Jae-Hyoung CHOI ,  Youn-Soo Kim ,  Jung-Hyeon Kim ,  Wan-Don Kim ,  Jae-Soon Lim ,  Sang-Yeol Kang

发明人： Jae-Hyoung CHOI ,  Youn-Soo Kim ,  Jung-Hyeon Kim ,  Wan-Don Kim ,  Jae-Soon Lim ,  Sang-Yeol Kang

IPC分类号： H01G4/008 ,  B32B9/04 ,  B05D5/12 ,  C23C14/34

CPC分类号： H01L23/5223 ,  H01L23/53261 ,  H01L28/56 ,  H01L28/91 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a multilayer structure and a method of forming the same, a conductive layer including a metal nitride and a dielectric layer positioned on a surface of the conductive layer and having a high dielectric constant. The metal nitride comprises one of niobium, vanadium and compositions thereof. Thus, the EOT and leakage current of the multilayer structure may be sufficiently improved.

摘要翻译： 在多层结构及其形成方法中，包括位于导电层表面上并具有高介电常数的金属氮化物和电介质层的导电层。 金属氮化物包括铌，钒及其组合物中的一种。 因此，可以充分提高多层结构的EOT和漏电流。

公开(公告)号：US20090085160A1

公开(公告)日：2009-04-02

申请号：US12238822

申请日：2008-09-26

申请人： Jong-cheol Lee ,  Jun-noh Lee ,  Ki-vin Im ,  Ki-yeon Park ,  Sung-hae Lee ,  Sang-yeol Kang

发明人： Jong-cheol Lee ,  Jun-noh Lee ,  Ki-vin Im ,  Ki-yeon Park ,  Sung-hae Lee ,  Sang-yeol Kang

IPC分类号： H01L29/92

CPC分类号： H01L29/51 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31641 ,  H01L21/31645 ,  H01L27/10852 ,  H01L28/65 ,  H01L29/513

摘要： Provided is a semiconductor device including an insulating layer of a cubic system or a tetragonal system, having good electrical characteristics. The semiconductor device includes a semiconductor substrate including an active region, a transistor that is formed in the active region of the semiconductor substrate, an interlevel insulating layer that is formed on the semiconductor substrate and a contact plug that is formed in the interlevel insulating layer and that is electrically connected to the transistor. The semiconductor device may include a lower electrode that is formed on the interlevel insulating layer and that is electrically connected to the contact plug, an upper electrode that is formed on the lower electrode and an insulating layer of a cubic system or a tetragonal system including a metal silicate layer. The insulating layer may be formed between the lower electrode and the upper electrode.

摘要翻译： 本发明提供一种半导体器件，其具有立方晶系或四方晶系的绝缘层，具有良好的电特性。 半导体器件包括：半导体衬底，包括有源区，形成在半导体衬底的有源区中的晶体管，形成在半导体衬底上的层间绝缘层和形成在层间绝缘层中的接触插塞;以及 其电连接到晶体管。 半导体器件可以包括形成在层间绝缘层上并且与电性连接的接触插塞的下电极，形成在下电极上的上电极和立方体系的绝缘层或包括 金属硅酸盐层。 绝缘层可以形成在下电极和上电极之间。

公开(公告)号：US20070148933A1

公开(公告)日：2007-06-28

申请号：US11512658

申请日：2006-08-30

申请人： Jin-Il Lee ,  Choong-Man Lee ,  Sung-Lae Cho ,  Ran-Ju Jung ,  Sang-Yeol Kang ,  Young-Lim Park

发明人： Jin-Il Lee ,  Choong-Man Lee ,  Sung-Lae Cho ,  Ran-Ju Jung ,  Sang-Yeol Kang ,  Young-Lim Park

IPC分类号： H01L21/20

CPC分类号： H01L21/32051 ,  H01L21/28562 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

摘要： A method of fabricating a phase-change random-access memory (RAM) device includes forming a chalcogenide material on a substrate. A bottom contact is formed under the chalcogenide material, the bottom contact comprising TiAlN. Forming the bottom contact includes performing an atomic layer deposition (ALD) process, the ALD process including introducing an NH3 source gas into a chamber in which the ALD process is being carried out, a flow amount of the NH3 gas being such that the resulting bottom contact has a chlorine content of less than 1 at %. The bottom contact can include TiAlN having a crystallinity in terms of full-width half-maximum (FWHM) of less than about 0.65 degree.

摘要翻译： 制造相变随机存取存储器（RAM）器件的方法包括在衬底上形成硫族化物材料。 在硫族化物材料下形成底部接触，底部接触包含TiAlN。 形成底部接触包括执行原子层沉积（ALD）工艺，ALD工艺包括将NH 3源气体引入到其中进行ALD工艺的室中，流动量为 NH 3气体使得所得底部接触物的氯含量小于1原子％。 底部接触可以包括具有小于约0.65度的全宽度半最大值（FWHM）的结晶度的TiAlN。

公开(公告)号：US20070111440A1

公开(公告)日：2007-05-17

申请号：US11581012

申请日：2006-10-16

申请人： Hyeong-Geun An ,  Hideki Horii ,  Sang-Yeol Kang

发明人： Hyeong-Geun An ,  Hideki Horii ,  Sang-Yeol Kang

IPC分类号： H01L21/00 ,  H01L21/336 ,  H01L29/94

CPC分类号： H01L45/144 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1293 ,  H01L45/165 ,  H01L45/1666

摘要： A phase changeable memory cell array region includes a lower interlayer insulating layer disposed on a semiconductor substrate. The region also includes a plurality of conductive plugs disposed through the lower interlayer insulating layer. The region also includes a phase changeable material pattern operably disposed on the lower interlayer insulating layer, the phase changeable pattern covering at least two of the plurality of conductive plugs, wherein the phase changeable material pattern includes a plurality of first regions in contact with one or more of the plurality of conductive plugs and at least one second region interposed between the plurality of the first regions, wherein the at least one second region has a lower thermal conductivity than the plurality of first regions. The phase changeable memory cell array region also includes an upper interlayer insulating layer covering at least one of the phase changeable material pattern and the lower interlayer insulating layer. The region also includes conductive patterns disposed through the upper interlayer insulating layer and electrically connected to a plurality of predetermined regions of the plurality of first regions.

摘要翻译： 相变存储单元阵列区域包括设置在半导体衬底上的下层间绝缘层。 该区域还包括穿过下层间绝缘层设置的多个导电插塞。 所述区域还包括可操作地设置在所述下层间绝缘层上的可相变材料图案，所述相变图案覆盖所述多个导电插塞中的至少两个，其中所述相变材料图案包括多个与第 多个导电插塞中的多个和插入在多个第一区域之间的至少一个第二区域，其中至少一个第二区域具有比多个第一区域更低的热导率。 相变存储单元阵列区域还包括覆盖相变材料图案和下层间绝缘层中的至少一个的上层间绝缘层。 该区域还包括通过上层间绝缘层设置并电连接到多个第一区域中的多个预定区域的导电图案。