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1.发明申请METHODS AND SYSTEMS TO SELECTIVELY BOOST AN OPERATING VOLTAGE OF, AND CONTROLS TO AN 8T BIT-CELL ARRAY AND/OR OTHER LOGIC BLOCKS 有权选择性地增加对8T位单元阵列和/或其他逻辑块的操作电压和控制的方法和系统公开(公告)号：US20150009751A1
公开(公告)日：2015-01-08
申请号：US14350546
申请日：2012-03-26
IPC分类号： G11C5/14 , G11C7/12 , G11C11/418 , G11C8/10 , G11C11/419
CPC分类号： G11C11/419 , G11C5/14 , G11C5/145 , G11C5/147 , G11C5/148 , G11C7/12 , G11C8/08 , G11C8/10 , G11C11/4074 , G11C11/412 , G11C11/417 , G11C11/418 , G11C13/0038 , G11C29/021 , G11C29/028 , G11C2207/2227
摘要： Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase.
摘要翻译： 提供多Vcc环境的方法和系统，例如选择性地提高逻辑块的工作电压和/或向逻辑块提供电平移位控制。 可以实现多Vcc环境以将Vmin限制逻辑块与单Vcc环境隔离，例如在单Vcc环境中减少Vmin和/或提高能量效率。 逻辑块可以包括寄存器文件的位单元，低级处理器高速缓存和/或其他存储器系统。 可以在读取模式期间升高单元Vcc，和/或写入字线（WWL）和/或读取字线（RWL）可以通过升压来断言。 字线解码器可以包括具有差分分离级逻辑的电压电平移位器和动态NAND，其可以包括NAND逻辑，保持器电路和用于基于电平转换器的延迟来延迟保持器控制的逻辑，以减少在 初始NAND评估阶段。
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2.发明授权Methods and systems to selectively boost an operating voltage of, and controls to an 8T bit-cell array and/or other logic blocks 有权选择性地提高8T位单元阵列和/或其他逻辑块的工作电压并控制其的方法和系统公开(公告)号：US09299395B2
公开(公告)日：2016-03-29
申请号：US14350546
申请日：2012-03-26
IPC分类号： G11C11/419 , G11C5/14 , G11C7/08 , G11C11/4074 , G11C11/417 , G11C7/12 , G11C8/10 , G11C11/418 , G11C13/00 , G11C29/02 , G11C11/412
CPC分类号： G11C11/419 , G11C5/14 , G11C5/145 , G11C5/147 , G11C5/148 , G11C7/12 , G11C8/08 , G11C8/10 , G11C11/4074 , G11C11/412 , G11C11/417 , G11C11/418 , G11C13/0038 , G11C29/021 , G11C29/028 , G11C2207/2227
摘要： Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase.
摘要翻译： 提供多Vcc环境的方法和系统，例如选择性地提高逻辑块的工作电压和/或向逻辑块提供电平移位控制。 可以实现多Vcc环境以将Vmin限制逻辑块与单Vcc环境隔离，例如在单Vcc环境中减少Vmin和/或提高能量效率。 逻辑块可以包括寄存器文件的位单元，低级处理器高速缓存和/或其他存储器系统。 可以在读取模式期间升高单元Vcc，和/或写入字线（WWL）和/或读取字线（RWL）可以通过升压来断言。 字线解码器可以包括具有差分分离级逻辑的电压电平移位器和动态NAND，其可以包括NAND逻辑，保持器电路和用于基于电平移位器的延迟来延迟保持器控制的逻辑，以减少在 初始NAND评估阶段。
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公开(公告)号：US07206249B2
公开(公告)日：2007-04-17
申请号：US10956195
申请日：2004-09-30
申请人： Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , James Tschanz , Stephen H. Tang , Vivek K. De
发明人： Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , James Tschanz , Stephen H. Tang , Vivek K. De
IPC分类号： G11C5/14
CPC分类号： G11C11/413
摘要： A method is described that comprises modulating the power consumption of an SRAM as a function of its usage at least by reaching, with help of a transistor, a voltage on a node within an operational amplifier's feedback loop. The voltage is beyond another voltage that the operational amplifier would drive the node to be without the help of the transistor. The voltage helps the feedback loop establish a voltage drop across a cell within the SRAM.
摘要翻译： 描述了一种方法，其包括至少通过在晶体管处达到运算放大器的反馈回路内的节点上的电压来调制作为其使用的函数的SRAM的功耗。 电压超过另一个电压，运算放大器将驱动节点没有晶体管的帮助。 电压有助于反馈回路在SRAM内的单元上建立一个压降。
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4.发明授权Methods and systems to read a magnetic tunnel junction (MTJ) based memory cell based on a pulsed read current 有权基于脉冲读取电流读取基于磁隧道结（MTJ）的存储单元的方法和系统公开(公告)号：US09455011B2
公开(公告)日：2016-09-27
申请号：US14350997
申请日：2012-03-25
申请人： Arijit Raychowdhury , David Kencke , Brian Doyle , Charles Kuo , James Tschanz , Fatih Hamzaoglu , Yih Wang , Roksana Golizadeh Mojarad
发明人： Arijit Raychowdhury , David Kencke , Brian Doyle , Charles Kuo , James Tschanz , Fatih Hamzaoglu , Yih Wang , Roksana Golizadeh Mojarad
CPC分类号： G11C11/165 , G11C5/12 , G11C11/1673 , G11C11/1693 , G11C2013/0052 , G11C2013/0071
摘要： Methods and systems to read a logic value stored in a magnetic tunnel junction (MTJ)-based memory cell based on a pulsed read current, with time between pulses to permit the MTJ to relax towards the magnetization orientation between the pulses, which may reduce build-up of momentum within the MTJ, and which may reduce and/or eliminate inadvertent re-alignment of a magnetization orientation. A sequence of symmetric and/or non-symmetric pulses may be applied to a wordline (WL) to cause a pre-charged bit line (BL) capacitance to discharge a pulsed read current through the MTJ, resulting in a corresponding sequence of voltage changes on the BL. The BL voltage changes may be integrated over the sequence of read current pulses, and a stored logic value may be determined based on the integrated voltage changes. The pre-charged BL capacitance may also serve as the voltage integrator.
摘要翻译： 基于脉冲读取电流读取存储在基于磁隧道结（MTJ）的存储单元中的逻辑值的方法和系统，脉冲之间的时间允许MTJ朝向脉冲之间的磁化取向松弛，这可以减少构建 - MTJ内的动量，并且其可以减少和/或消除磁化取向的无意重新对准。 对称和/或非对称脉冲的序列可以被施加到字线（WL），以使预充电位线（BL）电容放电通过MTJ的脉冲读取电流，从而产生相应的电压变化序列 在BL上。 可以在读取电流脉冲的序列上积分BL电压变化，并且可以基于积分的电压变化来确定存储的逻辑值。 预充电的BL电容也可以用作电压积分器。
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公开(公告)号：US08589706B2
公开(公告)日：2013-11-19
申请号：US11964551
申请日：2007-12-26
申请人： Ming Zhang , Chris Wilkerson , Greg Taylor , Randy J. Aksamit , James Tschanz
发明人： Ming Zhang , Chris Wilkerson , Greg Taylor , Randy J. Aksamit , James Tschanz
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/26 , G06F1/32 , G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F1/3293 , G06F12/0802 , G06F2212/1028 , Y02D10/13
摘要： Disclosed herein are approaches to reducing a guardband (margin) used for minimum voltage supply (Vcc) requirements for memory such as cache.
摘要翻译： 这里公开了减少用于诸如高速缓存的存储器的最小电压供应（Vcc）要求的保护带（余量）的方法。
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公开(公告)号：US20060262610A1
公开(公告)日：2006-11-23
申请号：US11134450
申请日：2005-05-23
申请人： Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Vivek De , James Tschanz , Stephen Tang
发明人： Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Vivek De , James Tschanz , Stephen Tang
IPC分类号： G11C5/14
摘要： A method and apparatus for reducing power consumption in integrated memory devices is provided. Banks of memory cells may be individually put into “sleep” mode via respective “sleep” transistors.
摘要翻译： 提供了一种降低集成存储器件功耗的方法和装置。 存储单元组可以通过相应的“睡眠”晶体管单独地进入“睡眠”模式。
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公开(公告)号：US20060164157A1
公开(公告)日：2006-07-27
申请号：US11038134
申请日：2005-01-21
申请人： James Tschanz , Stephen Tang , Victor Zia , Badarinath Kommandur , Siva Narendra , Vivek De
发明人： James Tschanz , Stephen Tang , Victor Zia , Badarinath Kommandur , Siva Narendra , Vivek De
IPC分类号： H01L29/861
CPC分类号： G05F3/205
摘要： A bias generator unit is provided that includes a central bias generator to provide a bias voltage, a local bias generator to receive the bias voltage and a reference voltage and to provide a forward body bias signal or a reverse body bias signal. The bias generator may include a charge pump to output (or provide) a reference voltage to a reference generator, which in turn provides reference signals to the central bias generator. As a result, the local bias generator may control the body bias signal provided by the local bias generator.
摘要翻译： 提供偏置发生器单元，其包括中心偏置发生器以提供偏置电压，局部偏置发生器以接收偏置电压和参考电压，并提供正向偏置信号或反向偏置信号。 偏置发生器可以包括电荷泵以将参考电压输出（或提供）到参考发生器，基准电压器又向中心偏置发生器提供参考信号。 结果，本地偏置发生器可以控制由局部偏置发生器提供的体偏置信号。
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公开(公告)号：US20060109028A1
公开(公告)日：2006-05-25
申请号：US11314236
申请日：2005-12-22
申请人： Maged Ghoneima , Peter Caputa , Muhammad Khellah , Ram Krishnamurthy , James Tschanz , Yibin Ye , Vivek De , Yehia Ismail
发明人： Maged Ghoneima , Peter Caputa , Muhammad Khellah , Ram Krishnamurthy , James Tschanz , Yibin Ye , Vivek De , Yehia Ismail
IPC分类号： H03K19/173
CPC分类号： G06F13/4072 , Y02D10/14 , Y02D10/151
摘要： An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second voltage different than the first voltage.
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公开(公告)号：US20060067109A1
公开(公告)日：2006-03-30
申请号：US10956195
申请日：2004-09-30
申请人： Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , James Tschanz , Stephen Tang , Vivek De
发明人： Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , James Tschanz , Stephen Tang , Vivek De
CPC分类号： G11C11/413
摘要： A method is described that comprises modulating the power consumption of an SRAM as a function of its usage at least by reaching, with help of a transistor, a voltage on a node within an operational amplifier's feedback loop. The voltage is beyond another voltage that the operational amplifier would drive the node to be without the help of the transistor. The voltage helps the feedback loop establish a voltage drop across a cell within the SRAM.
摘要翻译： 描述了一种方法，其包括至少通过在晶体管处达到运算放大器的反馈回路内的节点上的电压来调制作为其使用的函数的SRAM的功耗。 电压超过另一个电压，运算放大器将驱动节点没有晶体管的帮助。 电压有助于反馈回路在SRAM内的单元上建立一个压降。
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公开(公告)号：US20060066376A1
公开(公告)日：2006-03-30
申请号：US10953199
申请日：2004-09-28
申请人： Siva Narendra , James Tschanz , Vivek De , Nasser Kurd , Javed Barkatullah
发明人： Siva Narendra , James Tschanz , Vivek De , Nasser Kurd , Javed Barkatullah
IPC分类号： G06F1/04
CPC分类号： G06F1/324 , G06F1/06 , G06F1/206 , G06F1/3203 , Y02D10/126
摘要： Apparatus and systems, as well as methods and articles, may operate to select a microprocessor clock frequency responsive to a desired voltage and/or a desired temperature of operation.
摘要翻译： 装置和系统以及方法和物品可以操作以响应于期望电压和/或期望的操作温度来选择微处理器时钟频率。
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