公开(公告)号：US09272193B1

公开(公告)日：2016-03-01

申请号：US14471943

申请日：2014-08-28

Applicant: Hyung Jin Yim

Inventor： Hyung Jin Yim

IPC: A63B53/02 ,  A63B53/00 ,  A63B53/06 ,  A63B53/04

CPC classification number: A63B53/02 ,  A63B53/007 ,  A63B53/0487 ,  A63B53/065 ,  A63B2053/025 ,  A63B2053/0433 ,  A63B2053/0437

Abstract: The golf putter is configured such that the stop step of the rotary linkage is formed outwardly in an extended length to cause the lock screws to stop the rotary linkage from being rotated with a large torque at a position remote from the center of the threaded axle hole, so that when a user does not desire to change the lie angle in use, the adjusted lie angle is not changed for a long period of time.

Abstract translation: 高尔夫推杆构造成使得旋转连杆的停止步骤在延伸的长度上向外形成，以使得锁定螺钉停止旋转联动装置在远离螺纹轴孔的中心的位置以大的扭矩旋转 使得当用户不希望改变使用中的躺角时，调节后的角度长时间不变化。

公开(公告)号：US08383460B1

公开(公告)日：2013-02-26

申请号：US13243502

申请日：2011-09-23

Applicant: Myung Jin Yim

Inventor： Myung Jin Yim

IPC: H01L21/00

CPC classification number: H01L21/76898 ,  H01L21/6835 ,  H01L21/6836 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/14

Abstract: Methods are provided for fabricating integrated circuit systems that include forming integrated circuits in and on a semiconductor substrate. Via holes are etched into a front surface of the semiconductor substrate and are filled with a conductive material. A carrier wafer having a layer of adhesive thereon is provided and an imprinted pattern is formed in the layer of adhesive. The front surface of the semiconductor substrate is bonded to the carrier wafer with the patterned layer of adhesive. A portion of a back surface of the semiconductor substrate is removed to expose a portion of the conductive material and the thinned back surface is attached to a second substrate. The semiconductor substrate is then de-bonded from the carrier wafer.

Abstract translation: 提供了用于制造集成电路系统的方法，其包括在半导体衬底中以及半导体衬底上形成集成电路。 通孔蚀刻到半导体衬底的前表面并填充有导电材料。 提供其上具有粘合剂层的载体晶片，并且在粘合剂层中形成印刷图案。 半导体衬底的前表面与图案化的粘合剂层结合到载体晶片。 半导体衬底的后表面的一部分被去除以暴露导电材料的一部分，并且减薄的背表面附着到第二衬底。 然后将半导体衬底从载体晶片脱粘合。

公开(公告)号：US20110128711A1

公开(公告)日：2011-06-02

申请号：US12627937

申请日：2009-11-30

Applicant: Myung Jin Yim ,  Nanette Quevedo ,  Richard Strode

Inventor： Myung Jin Yim ,  Nanette Quevedo ,  Richard Strode

IPC: H05K7/00 ,  H01R43/00 ,  H01R43/02

CPC classification number: H05K1/181 ,  G06F1/16 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/315 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/48 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01068 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H05K3/341 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49179 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Embodiments include but are not limited to apparatuses and systems including semiconductor packages, e.g. memory packages, having a substrate or a first package, and a second package coupled to the substrate or the first package, wherein the second package includes at least one die and an underfill material disposed in a portion, but not an entirety, of an area between the package and the substrate or the first package. Other embodiments may be described and claimed.

Abstract translation: 实施例包括但不限于包括半导体封装的设备和系统。 存储器封装，具有衬底或第一封装，以及耦合到所述衬底或所述第一封装的第二封装，其中所述第二封装包括至少一个管芯和底部填充材料，所述底部填充材料设置在区域 在封装和衬底或第一封装之间。 可以描述和要求保护其他实施例。

公开(公告)号：US20100167466A1

公开(公告)日：2010-07-01

申请号：US12347800

申请日：2008-12-31

Applicant: Ravikumar Adimula ,  Myung Jin Yim

Inventor： Ravikumar Adimula ,  Myung Jin Yim

IPC: H01L21/98 ,  H05K7/00 ,  H05K3/34 ,  H05K3/30

CPC classification number: H05K3/323 ,  H01L23/3121 ,  H01L23/49811 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19043 ,  H05K2201/10719 ,  Y10T29/4913 ,  Y10T29/49144 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/01005 ,  H01L2924/01004 ,  H01L2924/01033

Abstract: An apparatus and method of making a package substrate with metal bumps is presented. The package substrate comprises a substrate base and a plurality of metal bumps which are formed on the substrate base. A microelectronic die may thereafter be attached to the package substrate. Also presented is a method for attaching the package substrate to a printed circuit board (PCB).

Abstract translation: 提出了一种制造具有金属凸块的封装衬底的装置和方法。 封装衬底包括衬底基底和形成在衬底基底上的多个金属凸块。 此后可以将微电子管芯附接到封装衬底。 还提出了一种将封装衬底附着到印刷电路板（PCB）的方法。

公开(公告)号：US07446384B2

公开(公告)日：2008-11-04

申请号：US11395157

申请日：2006-04-03

Applicant: Kyung-Wook Paik ,  Myung-Jin Yim ,  Ho-Young Son ,  Yong-Min Kwon

Inventor： Kyung-Wook Paik ,  Myung-Jin Yim ,  Ho-Young Son ,  Yong-Min Kwon

IPC: H01L27/14 ,  H01L31/00

CPC classification number: H01L31/02162 ,  H01L27/14618 ,  H01L27/1462 ,  H01L27/14625 ,  H01L27/14632 ,  H01L27/14687 ,  H01L31/0203 ,  H01L31/02325 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The present invention relates to an image sensor module and a manufacturing method thereof, especially to a wafer level chip size package (WL-CSP) realized by directly contacting an image sensor chip wafer to a glass wafer on which an IR filter coating layer is deposited, an electrode rearrangement and a dicing process, a miniaturized image sensor module using this wafer level chip size package (WL-CSP) and a method thereof. The CMOS image sensor module using a wafer level chip size package technology according to the present invention comprises: an image sensor chip wafer having a partition with a lattice structure formed at portions except an image sensing area; and a glass wafer with an IR filter coating layer and a metal electrode; and wherein the image sensor chip wafer and the glass wafer form an electric contact and a chip sealing by a flip-chip bonding; and wherein a solder bump and a non solder bump are formed after a metal wiring is rearranged on a lower surface of the glass wafer. According to the present invention, it is possible to realize a cheap wafer level chip size package (WL-CSP) using the existing wafer processing and the metal deposition processing equipments. Further, an image sensor module with smaller thickness and area than the existing CSP package can be realized. Moreover, an image sensor module with a smaller area than the existing COG package can be realized.

Abstract translation: 图像传感器模块及其制造方法技术领域本发明涉及一种图像传感器模块及其制造方法，特别涉及通过将图像传感器芯片晶片直接接触到其上沉积有IR滤光器涂层的玻璃晶片实现的晶片级芯片尺寸封装（WL-CSP） ，电极重排和切割处理，使用该晶片级芯片尺寸封装（WL-CSP）的小型化图像传感器模块及其方法。 使用根据本发明的晶片级芯片尺寸封装技术的CMOS图像传感器模块包括：图像传感器芯片晶片，具有形成在除了图像感测区域之外的部分处的格子结构的分隔; 和具有IR滤光器涂层和金属电极的玻璃晶片; 并且其中所述图像传感器芯片晶片和所述玻璃晶片通过倒装芯片接合形成电接触和芯片密封; 并且其中在金属布线重新布置在玻璃晶片的下表面上之后形成焊料凸块和非焊料凸块。 根据本发明，可以使用现有的晶片处理和金属沉积处理设备来实现廉价的晶片级芯片尺寸封装（WL-CSP）。 此外，可以实现具有比现有CSP封装更小的厚度和面积的图像传感器模块。 此外，可以实现具有比现有COG封装小的面积的图像传感器模块。

公开(公告)号：US20060135633A1

公开(公告)日：2006-06-22

申请号：US11263867

申请日：2005-11-02

Applicant: Kwang Lee ,  Jin Yim

Inventor： Kwang Lee ,  Jin Yim

IPC: C08J9/00 ,  C08L63/00

CPC classification number: C08J5/18 ,  C08J2383/04 ,  C08J2383/14 ,  H01B3/441

Abstract: A porous low-dielectric constant thin film with controlled solvent diffusion into pores of the porous thin film. The porous thin film i s formed from a composition including a porogen containing at least one π-π interacting functional group, a thermostable matrix precursor, and a solvent dissolving the porogen and the matrix precursor. The porous thin film thus formed has mesopores not smaller than 10 nm in size and has a solvent diffusion rate not higher than 30 μm2/sec. Due to the presence of the large pores, the porous thin film can greatly inhibit solvent diffusion into the pores of the thin film, which is encountered during wet processes, without substantial changes in dielectric constant, elastic modulus and hardness depending on the porosity of the thin film.

Abstract translation: 多孔低介电常数薄膜，其具有控制的溶剂扩散到多孔薄膜的孔中。 由包含至少一个π-π相互作用官能团的致孔剂的组合物形成多孔薄膜，热稳定性基质前体和溶解致孔剂和基质前体的溶剂。 由此形成的多孔薄膜的中孔的尺寸不小于10nm，溶剂扩散速率不高于30μm2 / sec。 由于存在大的孔，多孔薄膜可以极大地抑制在湿法中遇到的溶剂扩散到薄膜的孔中，而介电常数，弹性模量和硬度几乎不变，这取决于 薄膜。

公开(公告)号：US20050131190A1

公开(公告)日：2005-06-16

申请号：US10868222

申请日：2004-06-16

Applicant: Jae Lee ,  Jong Seon ,  Hyun Jeong ,  Jin Yim ,  Hyeon Shin

Inventor： Jae Lee ,  Jong Seon ,  Hyun Jeong ,  Jin Yim ,  Hyeon Shin

IPC: C07B61/00 ,  C07F7/08 ,  C07F7/18 ,  C07F7/21 ,  C08G77/04 ,  C08G77/50 ,  C08G77/60 ,  G03F7/075 ,  H01L21/312

CPC classification number: C08G77/50 ,  C07F7/0838 ,  C07F7/1804

Abstract: A novel multi-functional linear siloxane compound, a siloxane polymer prepared from the siloxane compound, and a process for forming a dielectric film by using the siloxane polymer. The linear siloxane polymer has enhanced mechanical properties (e.g., modulus), superior thermal stability, a low carbon content and a low hygroscopicity and is prepared by the homopolymerization of the linear siloxane compound or the copolymerization of the linear siloxane compound with another monomer. A dielectric film can be produced by heat-curing a coating solution containing the siloxane polymer which is highly reactive. The siloxane polymer prepared from the siloxane compound not only has satisfactory mechanical properties, thermal stability and crack resistance, but also exhibits a low hygroscopicity and excellent compatibility with pore-forming materials, which leads to a low dielectric constant. Furthermore, the siloxane polymer retains a relatively low carbon content but a high SiO2 content, resulting in its improved applicability to semiconductor devices. Therefore, the siloxane polymer is advantageously used as a material for dielectric films of semiconductor devices.

Abstract translation: 新型多功能直链硅氧烷化合物，由硅氧烷化合物制备的硅氧烷聚合物，以及通过使用硅氧烷聚合物形成电介质膜的方法。 线性硅氧烷聚合物具有增强的机械性能（例如模量），优异的热稳定性，低碳含量和低吸湿性，并且通过直链硅氧烷化合物的均聚或线性硅氧烷化合物与另一单体的共聚制备。 可以通过热固化含有高反应性的硅氧烷聚合物的涂布溶液来制造电介质膜。 由硅氧烷化合物制备的硅氧烷聚合物不仅具有令人满意的机械性能，热稳定性和抗裂性，而且具有低吸湿性和与成孔材料的优异相容性，导致低的介电常数。 此外，硅氧烷聚合物保持相对低的碳含量，但具有高的SiO 2含量，从而改善了对半导体器件的适用性。 因此，硅氧烷聚合物有利地用作半导体器件的介电膜的材料。

公开(公告)号：US20130078767A1

公开(公告)日：2013-03-28

申请号：US13243605

申请日：2011-09-23

Applicant: Myung Jin Yim

Inventor： Myung Jin Yim

IPC: H01L21/50

CPC classification number: H01L21/6836 ,  H01L21/76898 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68377 ,  H01L2221/68381 ,  H01L2224/11002 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/27334 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/12042 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2924/014 ,  H01L2924/00

Abstract: A method is provided for fabricating an integrated circuit system that includes fabricating a plurality of integrated circuits in and on a semiconductor substrate. Spaced apart solder bumps are attached to the plurality of integrated circuits, the solder bumps in electrical contact to components of the integrated circuits. A dicing tape having a layer of under-fill material thereon is provided and the semiconductor substrate is laminated to the dicing tape with the layer of under-fill material filling spaces between the solder bumps. The semiconductor substrate and layer of under-fill material are diced to singulate individual ones of the plurality of integrated circuits, and one of the individual ones of the plurality of integrated circuits is attached to a second substrate such as another integrated circuit chip or printed circuit board.

Abstract translation: 提供了一种用于制造集成电路系统的方法，该集成电路系统包括在半导体衬底中和半导体衬底上制造多个集成电路。 间隔开的焊料凸块连接到多个集成电路，焊料凸块与集成电路的部件电接触。 提供了具有其上的填充材料层的切割胶带，并且半导体衬底被层压到切割带上，并且在焊料凸块之间具有填充不足的填充空间层。 将半导体衬底和未填充材料层切割成单个多个集成电路中的单个集成电路，并且多个集成电路中的一个集成电路中的一个集成电路中的一个集成电路中的一个被附接到第二衬底，例如另一集成电路芯片或印刷电路 板。

公开(公告)号：US08344491B2

公开(公告)日：2013-01-01

申请号：US12347738

申请日：2008-12-31

Applicant: Ravikumar Adimula ,  Myung Jin Yim

Inventor： Ravikumar Adimula ,  Myung Jin Yim

IPC: H01L23/02

CPC classification number: H01L23/4985 ,  H01L23/3128 ,  H01L23/5387 ,  H01L24/50 ,  H01L24/86 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/16 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/06579 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/30105 ,  H01L2924/00

Abstract: A multi-die building block for a stacked-die package is described. The multi-die building block includes a flex tape having a first surface and a second surface, each surface including a plurality of electrical traces. A first die is coupled, through a first plurality of interconnects, to the plurality of electrical traces of the first surface of the flex tape. A second die is coupled, through a second plurality of interconnects, to the plurality of electrical traces of the second surface of the flex tape.

Abstract translation: 描述了用于堆叠管芯封装的多管芯构建块。 多模构造块包括具有第一表面和第二表面的柔性带，每个表面包括多个电迹线。 第一管芯通过第一多个互连件连接到柔性带的第一表面的多个电迹线。 第二管芯通过第二多个互连件连接到柔性带的第二表面的多个电迹线。

公开(公告)号：US20100164085A1

公开(公告)日：2010-07-01

申请号：US12347738

申请日：2008-12-31

Applicant: Ravikumar Adimula ,  Myung Jin Yim

Inventor： Ravikumar Adimula ,  Myung Jin Yim

IPC: H01L23/48 ,  H05K1/09 ,  H01L21/60

CPC classification number: H01L23/4985 ,  H01L23/3128 ,  H01L23/5387 ,  H01L24/50 ,  H01L24/86 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/16 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/06579 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/30105 ,  H01L2924/00

Abstract: A multi-die building block for a stacked-die package is described. The multi-die building block includes a flex tape having a first surface and a second surface, each surface including a plurality of electrical traces. A first die is coupled, through a first plurality of interconnects, to the plurality of electrical traces of the first surface of the flex tape. A second die is coupled, through a second plurality of interconnects, to the plurality of electrical traces of the second surface of the flex tape.

Abstract translation: 描述了用于堆叠管芯封装的多管芯构建块。 多模构造块包括具有第一表面和第二表面的柔性带，每个表面包括多个电迹线。 第一管芯通过第一多个互连件连接到柔性带的第一表面的多个电迹线。 第二管芯通过第二多个互连件连接到柔性带的第二表面的多个电迹线。