公开(公告)号：US5481205A

公开(公告)日：1996-01-02

申请号：US344393

申请日：1994-11-23

申请人： Robert C. Frye ,  Maureen Y. Lau ,  King L. Tai

发明人： Robert C. Frye ,  Maureen Y. Lau ,  King L. Tai

IPC分类号： H01L21/66 ,  G01R1/067 ,  G01R1/073 ,  G01R31/26 ,  H01L27/10 ,  H05K3/32 ,  G01R1/06 ,  H01L23/48

CPC分类号： H05K3/325 ,  G01R1/07307 ,  G01R1/06738 ,  H01L2924/0002

摘要： A given testing substrate for fast-testing many integrated-circuit electronic devices, one after the other, has a set of mutually insulated collated wiring areas that can be aligned with solder-bump I/O pads of the electronic devices. At the surface of each of the corrugated areas is located a layer that is an electrically conductive durable oxide, or that is itself durable, electrically conductive, and non-oxidizable. During testing, the solder-bump I/O pads of the electronic device being tested are aligned with and pressed against the corrugated wiring areas of the given substrate. Alternatively, the electronic devices being of the electrically programmable variety, such as EPROMs, programming voltages can be delivered to each of the devices, one after the other, through the corrugated wiring areas of a single substrate.

摘要翻译： 给定的用于快速测试许多集成电路电子器件的测试基板，一个接一个地具有一组可以与电子器件的焊料凸块I / O焊盘对准的相互绝缘的整理布线区域。 在每个波纹区域的表面上设置有导电耐用氧化物的层，或者其本身是耐用的，导电的和不可氧化的。 在测试期间，正在测试的电子器件的焊料凸块I / O焊盘与给定衬底的波纹布线区域对准并压紧。 或者，可以通过单个基板的波纹布线区域，一个接一个地将诸如EPROM的编程电压的电可编程品种的电子装置传送到每个装置。

公开(公告)号：US4670770A

公开(公告)日：1987-06-02

申请号：US582079

申请日：1984-02-17

申请人： King L. Tai

发明人： King L. Tai

IPC分类号： H01L23/14 ,  H01L23/485 ,  H01L23/538 ,  H01L23/64 ,  H01L29/06 ,  H01L29/04

CPC分类号： H01L24/02 ,  H01L23/147 ,  H01L23/538 ,  H01L23/5384 ,  H01L23/642 ,  H01L29/0657 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/01067 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/10157 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15156 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107

摘要： In the interest of enhanced yield in the manufacture of "wafer-scale" integrated circuits an assembly of integrated circuit chips is made by placing chips on a substrate. Chips have beveled edges as produced by crystallographically anisotropic chemical etching, and the substrate has wells, grooves, or openings having sloping walls. Chips are positioned on the substrate by bringing sloping walls and beveled edges in juxtaposition, and circuitry on chips is connected to circuitry on the substrate.

摘要翻译： 为了在“晶片级”集成电路的制造中提高产量的优点，通过将芯片放置在衬底上来制成集成电路芯片的组件。 芯片具有通过晶体学各向异性化学蚀刻产生的斜边，并且基板具有具有倾斜壁的孔，凹槽或开口。 通过使倾斜的壁和倾斜的边缘并置来将芯片定位在基板上，并且芯片上的电路连接到基板上的电路。

公开(公告)号：US4496448A

公开(公告)日：1985-01-29

申请号：US541459

申请日：1983-10-13

申请人： King L. Tai ,  Frederick Vratny

发明人： King L. Tai ,  Frederick Vratny

IPC分类号： H01L21/302 ,  H01J37/32 ,  H01L21/3065 ,  C23C15/00

CPC分类号： H01J37/32174 ,  H01J37/32082 ,  H01J37/3299 ,  H01J2237/3341 ,  H01J2237/3345

摘要： A method and apparatus for fabricating a device is disclosed, which method involves a new reactive ion etching technique. Both a high etch rate and, for example, a high etch selectivity are simultaneously achieved with the inventive reactive ion etching technique by discharging an electrode of the reactive ion etching apparatus in response to a preselected criterion, e.g., a magnitude of a DC bias at said electrode which equals, or exceeds, a preselected value.

摘要翻译： 公开了一种用于制造器件的方法和装置，该方法包括新的反应离子蚀刻技术。 通过本发明的反应离子蚀刻技术，通过根据预先选择的标准放电反应离子蚀刻设备的电极，例如，高的蚀刻速率和例如高的蚀刻选择性 所述电极等于或超过预选值。

公开(公告)号：US4454221A

公开(公告)日：1984-06-12

申请号：US366646

申请日：1982-04-08

申请人： Cheng-Hsuan Chen ,  Edith C. Ong ,  James C. Phillips ,  King L. Tai

发明人： Cheng-Hsuan Chen ,  Edith C. Ong ,  James C. Phillips ,  King L. Tai

IPC分类号： H01L21/306 ,  G03F7/004 ,  G03F7/20 ,  G03F7/32 ,  H01L21/027 ,  H01L21/311 ,  G03C5/00

CPC分类号： G03F7/0043 ,  G03F7/32 ,  H01L21/31111

摘要： A method for enhancing linewidth control during the patterning of a substrate with a resist is disclosed. Resists used in the invention have chemically separated structures characterized by two types of regions of different chemical composition, which different types of regions are interspersed among each other. Because the resists used in the present invention have chemically separated structures, anisotropic wet development of these resists is achievable with an appropriate bicomponent wet developer. Consequently, after exposure, the image formed in a thin, upper layer of the resist is transferred with vertical walls through the thickness of the resist.

摘要翻译： 公开了一种在用抗蚀剂图案化衬底的过程中增强线宽控制的方法。 用于本发明的抗蚀剂具有化学分离的结构，其特征在于两种不同化学组成的区域，其中不同类型的区域彼此散布。 因为本发明中使用的抗蚀剂具有化学分离的结构，所以用适当的双组分湿式显影剂可以实现这些抗蚀剂的各向异性湿法显影。 因此，在曝光之后，形成在抗蚀剂的较薄上层的图像通过抗蚀剂的厚度以垂直壁转印。

公开(公告)号：US06313719B1

公开(公告)日：2001-11-06

申请号：US09522450

申请日：2000-03-09

申请人： Ron Barnett ,  Yee Leng Low ,  Zhengxiang Ma ,  King L Tai ,  Hui Wu

发明人： Ron Barnett ,  Yee Leng Low ,  Zhengxiang Ma ,  King L Tai ,  Hui Wu

IPC分类号： H01P1203

CPC分类号： H01P1/20372

摘要： A bandpass planar filter (110) comprises a signal input and a signal output (116), and one or more resonator elements (112, 114) coupled serially end-to-end between the input and the output across gaps (118) that separate the elements from the input, the output, and from each other. The resonator elements form a serpentine shape such that at least two portions of the serpentine shape are positioned side-by-side parallel to each other separated by a spacing (120). The side-by-side portions effect additional coupling between the resonator elements that forms a notch (transmission zero) (204) in the passband (200) of the filter. The input, output, and resonator elements are etched into one surface (106) of a PC board (102); the other surface (104) of the PC board forms a ground plane of the filter, and the substrate (103) of the PC board forms a dielectric of the filter.

摘要翻译： 带通平面滤波器（110）包括信号输入端和信号输出端（116），以及一个或多个谐振元件（112,114），它们跨接在间隔（118）上的输入端和输出端之间端对端地串联连接， 来自输入，输出和彼此的元素。 谐振器元件形成蛇形形状，使得蛇形形状的至少两部分彼此平行地彼此平行地间隔开间隔（120）。 并排部分影响在滤波器的通带（200）中形成陷波（传输零点）（204）的谐振元件之间的附加耦合。 输入，输出和谐振器元件被蚀刻到PC板（102）的一个表面（106）中; PC板的另一个表面（104）形成滤波器的接地平面，并且PC板的基板（103）形成滤波器的电介质。

公开(公告)号：US5622305A

公开(公告)日：1997-04-22

申请号：US438296

申请日：1995-05-10

申请人： Donald D. Bacon ,  Cheng-Hsuan Chen ,  Ho S. Chen ,  Avishay Katz ,  King L. Tai

发明人： Donald D. Bacon ,  Cheng-Hsuan Chen ,  Ho S. Chen ,  Avishay Katz ,  King L. Tai

IPC分类号： B23K35/00 ,  H01L21/58 ,  H01L23/14 ,  H01L23/373 ,  B23K31/02 ,  B23K1/20

CPC分类号： H01L24/83 ,  B23K35/001 ,  H01L23/147 ,  H01L23/3732 ,  H01L24/29 ,  B23K2035/008 ,  B23K35/007 ,  H01L2224/04026 ,  H01L2224/2908 ,  H01L2224/29101 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/83193 ,  H01L2224/8385 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01041 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/07802 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  Y10T428/12819

摘要： A method for bonding one body to another, such as a laser device to a submount, uses a metallic layer composed of a Group VB metal, such as niobium, sandwiched between a non-metallic layer and solder layer formed by an approximate Au-Sn eutectic layer. Advantageously the Group VB layer is formed at a submount temperature of less than approximately 201.degree. C., advantageously less than approximately 125.degree. C., and preferably less than approximately 101.degree. C.--advantageously to a thickness in the approximate range 0.05 .mu.m to 0.2 .mu.m, or even thinner if pinholes do not develop. The non-metallic layer is located on one of the bodies, and the other body has a metallic coating advantageously capped with an Au layer.

摘要翻译： 将一体与另一体接合的方法，例如激光装置到基台，使用由诸如铌的VB族金属组成的金属层，夹在非金属层和由近似Au-Sn形成的焊料层之间 共晶层。 有利地，VB族VB层形成在小于约201℃，有利地小于约125℃，优选小于约101℃的底层温度下，有利地为约0.05μm的厚度 至0.2μm，如果针孔不发展，甚至更薄。 非金属层位于其中一个主体上，另一个主体具有有利于用Au层覆盖的金属涂层。

公开(公告)号：US5564617A

公开(公告)日：1996-10-15

申请号：US479587

申请日：1995-06-07

申请人： Yinon Degani ,  Thomas D. Dudderar ,  King L. Tai

发明人： Yinon Degani ,  Thomas D. Dudderar ,  King L. Tai

IPC分类号： H01L21/48 ,  H01L21/60 ,  H01L25/04 ,  H01L25/18 ,  H05K3/12 ,  H05K3/34 ,  B23K3/06

CPC分类号： H01L24/81 ,  H01L21/4867 ,  H01L24/75 ,  H05K3/3484 ,  H01L2224/1132 ,  H01L2224/16 ,  H01L2224/742 ,  H01L2224/75 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30107 ,  H05K2201/10674 ,  H05K2203/048 ,  H05K3/1216 ,  H05K3/3431 ,  H05K3/3436 ,  H05K3/3463

摘要： A multichip module is assembled using flip-chip bonding technology, a stencil printable solder paste and standard surface mount equipment for interconnecting signaling input/output contact pads on devices within such a multichip module. The disclosed assembly process makes the heretofore difficult and expensive flip chip bonding technique achievable at low cost. The flip chip bonding technique is simplified by use of a solder paste which includes desirable reflow alignment, fluxing and printability characteristics. These desirable characteristics allow the assembly process to be further economically achieved by permitting the use of standard surface mount equipment in the process. High volume production of standard inexpensive modules are thus possible through this process while also achieving the advantage of high density interconnections afforded through the flip-chip bonding technology.

摘要翻译： 多芯片模块使用倒装芯片焊接技术组装，模板可印刷焊膏和标准表面贴装设备，用于在这种多芯片模块内的器件上互连信号输入/输出接触焊盘。 所公开的组装过程使得迄今为止难以实现并且昂贵的倒装芯片接合技术以低成本实现。 通过使用包括期望的回流对准，助熔和可印刷性特征的焊膏来简化倒装芯片接合技术。 这些期望的特性允许通过允许在该过程中使用标准表面贴装设备来进一步经济地实现组装过程。 因此，可以通过该方法大量生产标准廉价的模块，同时还实现了通过倒装芯片接合技术提供的高密度互连的优点。

公开(公告)号：US5461333A

公开(公告)日：1995-10-24

申请号：US200986

申请日：1994-02-24

申请人： Joseph H. Condon ,  Robert C. Frye ,  Thaddeus J. Gabara ,  King L. Tai ,  Scott C. Knauer, deceased ,  Carroll H. Knauer, executor

发明人： Joseph H. Condon ,  Robert C. Frye ,  Thaddeus J. Gabara ,  King L. Tai ,  Scott C. Knauer, deceased ,  Carroll H. Knauer, executor

IPC分类号： H03K3/012 ,  H03K3/356 ,  H03K17/10 ,  H03K17/687

CPC分类号： H01L25/0655 ,  H03K3/012 ,  H03K3/356052 ,  H03K3/356147 ,  H01L2224/16225 ,  H01L2924/13091

摘要： A multi-chip module is composed of two or more integrated-circuit chips located on a substrate such as a dielectrically coated silicon substrate. The chips are interconnected by means of transmission wiring lines. At least some of the chips contain one or more input buffer circuits, each composed of two branches ("legs"). Each such branch contains, in one embodiment, an n-channel MOS transistor connected in series with a pair of series-connected p-channel MOS transistors--whereby, in each such branch, one of the p-channel MOS transistors is located between (intermediate) the other of the p-channel MOS transistors and the n-channel MOS transistor of that same branch. On the other hand, in each buffer circuit, the intermediate p-channel MOS transistors of both branches are cross-coupled. Each of the n-channel MOS transistors is connected in a common gate configuration to receive one of the complementary input signals coming from the transmission wiring lines, and the other of the p-channel transistors in each branch is connected in a common source configuration to receive the other of the complementary input signals.

摘要翻译： 多芯片模块由位于诸如介电涂覆的硅衬底的衬底上的两个或多个集成电路芯片组成。 芯片通过传输线路相互连接。 至少一些芯片包含一个或多个输入缓冲器电路，每个由两个分支（“支脚”）组成。 每个这样的分支在一个实施例中包含与一对串联连接的p沟道MOS晶体管串联连接的n沟道MOS晶体管，由此在每个这样的分支中，一个p沟道MOS晶体管位于（ 中间）另一个p沟道MOS晶体管和同一分支的n沟道MOS晶体管。 另一方面，在每个缓冲电路中，两个分支的中间p沟道MOS晶体管是交叉耦合的。 每个n沟道MOS晶体管以公共栅极配置连接以接收来自传输布线的互补输入信号之一，并且每个分支中的另一个p沟道晶体管以公共源配置连接到 接收另一个互补输入信号。

公开(公告)号：US4896937A

公开(公告)日：1990-01-30

申请号：US227220

申请日：1988-08-02

申请人： Richard T. Kraetsch ,  Richard J. Pimpinella ,  Leonard W. Schaper ,  King L. Tai

发明人： Richard T. Kraetsch ,  Richard J. Pimpinella ,  Leonard W. Schaper ,  King L. Tai

IPC分类号： G02B6/35 ,  G02B6/36

CPC分类号： G02B6/3572 ,  G02B6/3508 ,  G02B6/355 ,  G02B6/3582 ,  G02B6/3636 ,  G02B6/3652 ,  G02B6/3692

摘要： A precisely aligned optical fiber switch assembly. A base member has a vee groove for supporting a fixed optical fiber and a second optical fiber in optical alignment with the fixed fiber. The groove contains sections of different dimensions that receive and align sheathed portions of the fibers and groove sections that receive and align unsheathed portions of the fibers. First aligning means on the base member longitudinally position the fixed and second fibers in the groove. Covering means mate with the base member for covering at least part of the sheathed portions of the fibers. Aligning means position the covering means precisely with respect to the base member.

摘要翻译： 精密对准的光纤开关组件。 基座构件具有用于支撑固定光纤的vee槽和与固定光纤对准的第二光纤。 凹槽包含不同尺寸的部分，其接收和对准纤维的护套部分和容纳和对准纤维未固化部分的凹槽部分。 基体上的第一对准装置将固定和第二纤维纵向定位在槽中。 覆盖装置与基部构件配合以覆盖纤维的至少一部分护套部分。 对准装置将覆盖装置相对于基座构件精确地定位。

公开(公告)号：US4767695A

公开(公告)日：1988-08-30

申请号：US57682

申请日：1987-05-28

申请人： Edith T. T. Ong ,  King L. Tai ,  Yiu-Huen Wong

发明人： Edith T. T. Ong ,  King L. Tai ,  Yiu-Huen Wong

IPC分类号： G03F7/004 ,  G03F7/16 ,  G03F7/18 ,  G03C5/00

CPC分类号： G03F7/167 ,  G03F7/0043 ,  G03F7/18

摘要： A new method for lithographically patterning nonplanar substrates is disclosed. In accordance with this method, a nonplanar substrate surface is patterned by initially substantially conformably coating the surface with a resist. Conformality is achieved by depositing the resist either from the vapor phase or from a mist. In addition, the motions of the constituents of the vapor or mist should be sufficiently random so that the angular flux distribution at any point on the nonplanar substrate surface to be coated is substantially identical to that at any other point to be coated.

摘要翻译： 公开了一种用于平版印刷非平面基板的新方法。 根据这种方法，通过最初基本上顺应地用抗蚀剂涂覆表面来对非平面衬底表面进行构图。 通过从气相或雾中沉积抗蚀剂来实现一致性。 此外，蒸汽或雾的成分的运动应该是非常随机的，使得待涂覆的非平面基底表面上的任何点处的角通量分布基本上与待涂覆的任何其它点相同。