公开(公告)号：US10186500B2

公开(公告)日：2019-01-22

申请号：US15357741

申请日：2016-11-21

Applicant: Seung-Kwan Ryu ,  Yonghwan Kwon ,  Yun Seok Choi ,  Chajea Jo ,  Taeje Cho

Inventor： Seung-Kwan Ryu ,  Yonghwan Kwon ,  Yun Seok Choi ,  Chajea Jo ,  Taeje Cho

IPC: H01L25/10 ,  H01L25/00

Abstract: A semiconductor package includes upper and lower semiconductor chip packages, and a redistribution wiring layer pattern interposed between the packages. The lower package includes a molding layer in which at least one chip is embedded, and has a top surface and an inclined sidewall surface along which the redistribution wiring layer pattern is formed. The upper and lower packages are electrically connected to through the redistribution wiring layer pattern. A first package may be formed by a wafer level packaging technique and may include a redistribution wiring layer as a substrate, a semiconductor chip disposed on the redistribution wiring layer, and a molding layer on which the lower package, redistribution wiring layer pattern and upper package are disposed.

公开(公告)号：USD742900S1

公开(公告)日：2015-11-10

申请号：US29429141

申请日：2012-08-07

Applicant: Jangwon Seo ,  Woo-Seok Hwang ,  Hee-Jeong Bae ,  Yoojin Choi ,  YongHwan Kwon ,  Myungkwan Choi

Designer： Jangwon Seo ,  Woo-Seok Hwang ,  Hee-Jeong Bae ,  Yoojin Choi ,  YongHwan Kwon ,  Myungkwan Choi

公开(公告)号：USD734347S1

公开(公告)日：2015-07-14

申请号：US29429146

申请日：2012-08-07

Applicant: Yoojin Choi ,  YongHwan Kwon ,  Jangwon Seo ,  Woo-Seok Hwang ,  Hee-Jeong Bae ,  Myungkwan Choi

Designer： Yoojin Choi ,  YongHwan Kwon ,  Jangwon Seo ,  Woo-Seok Hwang ,  Hee-Jeong Bae ,  Myungkwan Choi

公开(公告)号：US20120074566A1

公开(公告)日：2012-03-29

申请号：US13188069

申请日：2011-07-21

Applicant: HanShin Youn ,  Yonghwan Kwon ,  YoungHoon Ro ,  Woojae Kim ,  Sungwoo Park

Inventor： HanShin Youn ,  Yonghwan Kwon ,  YoungHoon Ro ,  Woojae Kim ,  Sungwoo Park

IPC: H01L23/498 ,  H01L23/48

CPC classification number: H01L24/03 ,  H01L21/563 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/48 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/50 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An example embodiment relates to a semiconductor package. The semiconductor package includes a first substrate including a first pad, a second substrate upwardly spaced apart from the first substrate and including a second pad opposite to the first pad. At least one electrode is coupled between the first pad and the second pad. The semiconductor package includes a guide ring formed at a periphery of the electrode between the first substrate and the second substrate.

Abstract translation: 示例性实施例涉及半导体封装。 半导体封装包括第一衬底，其包括第一焊盘，与第一衬底向上间隔开的第二衬底，并且包括与第一焊盘相对的第二焊盘。 至少一个电极耦合在第一焊盘和第二焊盘之间。 半导体封装包括形成在第一基板和第二基板之间的电极的周边处的引导环。

公开(公告)号：US08105934B2

公开(公告)日：2012-01-31

申请号：US12461459

申请日：2009-08-12

Applicant: Yonghwan Kwon ,  Chungsun Lee ,  Sayoon Kang

Inventor： Yonghwan Kwon ,  Chungsun Lee ,  Sayoon Kang

IPC: H01L21/44

CPC classification number: H01L24/11 ,  H01L24/02 ,  H01L24/13 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/136 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014

Abstract: A semiconductor device employing the bump structure includes a plurality of bump structures arrayed along a substrate in a first direction. Each bump structure has a width in the first direction greater than a pitch gap between successively arrayed bump structures, and at least one bump structure has a sidewall facing in the first direction that is non-conductive.

Abstract translation: 采用该凸块结构的半导体器件包括在第一方向上沿衬底排列的多个凸块结构。 每个凸块结构在第一方向上的宽度大于连续排列的凸起结构之间的间距间隙，并且至少一个凸块结构具有面向不导通的第一方向的侧壁。

公开(公告)号：USD749605S1

公开(公告)日：2016-02-16

申请号：US29429138

申请日：2012-08-07

Applicant: Yoojin Choi ,  YongHwan Kwon ,  Jangwon Seo ,  Woo-Seok Hwang ,  Hee-Jeong Bae ,  Myungkwan Choi

Designer： Yoojin Choi ,  YongHwan Kwon ,  Jangwon Seo ,  Woo-Seok Hwang ,  Hee-Jeong Bae ,  Myungkwan Choi

公开(公告)号：US09142498B2

公开(公告)日：2015-09-22

申请号：US13917000

申请日：2013-06-13

Applicant: Boin Noh ,  Yonghwan Kwon ,  Sun-Hee Park

Inventor： Boin Noh ,  Yonghwan Kwon ,  Sun-Hee Park

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/49811 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05558 ,  H01L2224/05561 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/381 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/00012 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/01023 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/0103 ,  H01L2924/01058 ,  H01L2224/05552 ,  H01L2924/00

Abstract: An electrical interconnection can be provided using a bump stack including at least two solder bumps which are stacked on one another and at least one intermediate layer interposed between the at least stacked two solder bumps.

Abstract translation: 可以使用包括彼此堆叠的至少两个焊料凸块的凸起堆叠以及置于至少堆叠的两个焊料凸块之间的至少一个中间层来提供电互连。

公开(公告)号：USD735220S1

公开(公告)日：2015-07-28

申请号：US29429156

申请日：2012-08-07

Applicant: Jangwon Seo ,  Yoojin Choi ,  Hee-Jeong Bae ,  Myungkwan Choi ,  YongHwan Kwon ,  Woo-Seok Hwang

Designer： Jangwon Seo ,  Yoojin Choi ,  Hee-Jeong Bae ,  Myungkwan Choi ,  YongHwan Kwon ,  Woo-Seok Hwang

公开(公告)号：USD734346S1

公开(公告)日：2015-07-14

申请号：US29429145

申请日：2012-08-07

Applicant: Yoojin Choi ,  Jangwon Seo ,  Woo-Seok Hwang ,  YongHwan Kwon ,  Myungkwan Choi

Designer： Yoojin Choi ,  Jangwon Seo ,  Woo-Seok Hwang ,  YongHwan Kwon ,  Myungkwan Choi

公开(公告)号：USD733726S1

公开(公告)日：2015-07-07

申请号：US29429152

申请日：2012-08-07

Applicant: Jangwon Seo ,  Hee-Jeong Bae ,  YongHwan Kwon ,  Yoojin Choi ,  Woo-Seok Hwang ,  Myungkwan Choi

Designer： Jangwon Seo ,  Hee-Jeong Bae ,  YongHwan Kwon ,  Yoojin Choi ,  Woo-Seok Hwang ,  Myungkwan Choi