公开(公告)号：US08859422B2

公开(公告)日：2014-10-14

申请号：US13359138

申请日：2012-01-26

申请人： Tadahiro Ishizaka ,  Atsushi Gomi ,  Takara Kato ,  Osamu Yokoyama ,  Takashi Sakuma ,  Chiaki Yasumuro ,  Hiroyuki Toshima ,  Tatsuo Hatano ,  Yasushi Mizusawa ,  Masamichi Hara ,  Kenzi Suzuki

发明人： Tadahiro Ishizaka ,  Atsushi Gomi ,  Takara Kato ,  Osamu Yokoyama ,  Takashi Sakuma ,  Chiaki Yasumuro ,  Hiroyuki Toshima ,  Tatsuo Hatano ,  Yasushi Mizusawa ,  Masamichi Hara ,  Kenzi Suzuki

IPC分类号： H01L21/44

CPC分类号： H01L21/02104 ,  C23C14/025 ,  C23C14/046 ,  C23C14/345 ,  C23C14/541 ,  C23C14/5806 ,  C23C16/16 ,  H01J37/32899 ,  H01J37/34

摘要： A method of forming a Cu wiring in a trench or hole formed in a substrate is provided. The method includes forming a barrier film on the surface of the trench or hole, forming a Ru film on the barrier film, and embedding Cu in the trench or hole by forming a Cu film on the Ru film using PVD while annealing the substrate such that migration of copper into the trench or hole occurs.

摘要翻译： 提供了一种在衬底中形成的沟槽或孔中形成Cu布线的方法。 该方法包括在沟槽或孔的表面上形成阻挡膜，在阻挡膜上形成Ru膜，并且通过在使衬底退火的同时在PVD膜上形成Cu膜而将Cu嵌入沟槽或孔中，使得 发生铜进入沟槽或孔的迁移。

公开(公告)号：US08399353B2

公开(公告)日：2013-03-19

申请号：US13081172

申请日：2011-04-06

申请人： Tadahiro Ishizaka ,  Atsushi Gomi ,  Takara Kato ,  Osamu Yokoyama ,  Takashi Sakuma ,  Chiaki Yasumuro ,  Hiroyuki Toshima ,  Tatsuo Hatano ,  Yasushi Mizusawa ,  Masamichi Hara

发明人： Tadahiro Ishizaka ,  Atsushi Gomi ,  Takara Kato ,  Osamu Yokoyama ,  Takashi Sakuma ,  Chiaki Yasumuro ,  Hiroyuki Toshima ,  Tatsuo Hatano ,  Yasushi Mizusawa ,  Masamichi Hara

IPC分类号： H01L21/768

CPC分类号： C23C16/16 ,  C23C14/024 ,  C23C14/025 ,  C23C14/046 ,  C23C14/165 ,  C23C14/345 ,  C23C14/568 ,  C23C14/5873 ,  C23C16/0272 ,  C23C16/045 ,  C23C16/54 ,  C23C16/56 ,  C23C28/023 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76846 ,  H01L21/76882 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a Cu wiring in a trench or hole formed in a substrate is provided. The method includes forming a barrier film on the surface of the trench or hole, forming a Ru film on the barrier film, and embedding copper in the trench or hole by forming a Cu film on the Ru film using PVD while heating the substrate such that migration of copper into the trench or hole occurs.

摘要翻译： 提供了一种在衬底中形成的沟槽或孔中形成Cu布线的方法。 该方法包括在沟槽或孔的表面上形成阻挡膜，在阻挡膜上形成Ru膜，并通过在加热衬底的同时在PVD膜上形成Cu膜，将铜包埋在沟槽或孔中，使得 发生铜进入沟槽或孔的迁移。

公开(公告)号：US20130237053A1

公开(公告)日：2013-09-12

申请号：US13876682

申请日：2011-09-26

申请人： Tadahiro Ishizaka ,  Takashi Sakuma ,  Tatsuo Hatano ,  Osamu Yokoyama ,  Atsushi Gomi ,  Chiaki Yasumuro ,  Toshihiko Fukushima ,  Hiroyuki Toshima ,  Masaya Kawamata ,  Yasushi Mizusawa ,  Takara Kato

发明人： Tadahiro Ishizaka ,  Takashi Sakuma ,  Tatsuo Hatano ,  Osamu Yokoyama ,  Atsushi Gomi ,  Chiaki Yasumuro ,  Toshihiko Fukushima ,  Hiroyuki Toshima ,  Masaya Kawamata ,  Yasushi Mizusawa ,  Takara Kato

IPC分类号： H01L21/768 ,  H01J37/34

CPC分类号： H01L21/768 ,  C23C14/021 ,  C23C14/024 ,  C23C14/14 ,  C23C14/345 ,  C23C14/3492 ,  C23C14/541 ,  C23C14/542 ,  H01J37/34 ,  H01L21/2855 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76882

摘要： A film forming method which generates metal ions from a metal target with a plasma in a processing chamber and attracts the metal ions with a bias to deposit a metal thin film on a target object wherein trenches are formed. The method includes: generating metal ions from a target and attracting the metal ions into a target object with a bias to form a base film in a trench; ionizing a rare gas with the bias in a state where no metal ion is generated and attracting the generated ions into the target object to etch the base film; and plasma sputtering the target to generate metal ions and attracting the metal ions into the object with a high frequency power for bias to deposit a main film as a metal film, while reflowing the main film by heating.

摘要翻译： 一种在处理室中从具有等离子体的金属靶产生金属离子的薄膜形成方法，并且在偏压下吸引金属离子以在形成有沟槽的目标物体上沉积金属薄膜。 该方法包括：从靶产生金属离子并以偏压将金属离子吸引到目标物体中，以在沟槽中形成基膜; 在不产生金属离子的状态下以偏压电离稀有气体，并将产生的离子吸引到目标物体中以蚀刻基膜; 并且等离子体溅射靶以产生金属离子并以高频功率将金属离子吸引到物体中以偏压沉积作为金属膜的主膜，同时通过加热回流主膜。

公开(公告)号：US20120247949A1

公开(公告)日：2012-10-04

申请号：US13433527

申请日：2012-03-29

申请人： Takashi SAKUMA ,  Tadahiro Ishizaka ,  Tatsuo Hatano ,  Shiro Hayashi ,  Toshiaki Fujisato ,  Hiroyuki Yokohara ,  Hiroyuki Toshima

发明人： Takashi SAKUMA ,  Tadahiro Ishizaka ,  Tatsuo Hatano ,  Shiro Hayashi ,  Toshiaki Fujisato ,  Hiroyuki Yokohara ,  Hiroyuki Toshima

IPC分类号： C23C14/34

CPC分类号： H01L21/2855 ,  C23C14/046 ,  C23C14/185 ,  C23C14/345 ,  C23C14/5833 ,  C23C14/5873 ,  C23C14/5893 ,  C23C16/509 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76873

摘要： A film forming method includes depositing a metal thin film on a target substrate by generating an inductively coupled plasma in a processing chamber while introducing a plasma generating gas in the processing chamber with the substrate disposed on a placing table, by supplying DC power to a metal target from a DC power source, and by applying high-frequency bias to the placing table. A resputtering method includes resputtering the deposited metal thin film by stopping the generating of the inductively coupled plasma, by stopping the power supply from the DC power source, and by applying the high-frequency bias to the placing table while introducing the plasma generating gas in the processing chamber to form a capacitively coupled plasma in the processing chamber and by attracting ions of the plasma generating gas to the target substrate where the metal thin film is deposited.

摘要翻译： 一种成膜方法，包括通过在处理室中产生电感耦合等离子体，同时在处理室中引入等离子体产生气体，其中衬底设置在放置台上，通过向金属提供DC电力，在目标衬底上沉积金属薄膜 来自直流电源的目标，以及通过对放置台应用高频偏压。 再溅射方法包括：通过停止来自直流电源的电力供给，通过停止产生电感耦合等离子体，并将高频偏压施加到放置台，同时将等离子体产生气体引入到 所述处理室在所述处理室中形成电容耦合的等离子体，并且通过将所述等离子体产生气体的离子吸附到沉积金属薄膜的目标衬底上。

公开(公告)号：US20110017706A1

公开(公告)日：2011-01-27

申请号：US12668106

申请日：2008-07-10

申请人： Tetsuro Takahashi ,  Yutaka Fujino ,  Hiroyuki Toshima ,  Atsushi Kubo ,  Song Yun Kang ,  Peter Ventzek ,  Sumie Segawa

发明人： Tetsuro Takahashi ,  Yutaka Fujino ,  Hiroyuki Toshima ,  Atsushi Kubo ,  Song Yun Kang ,  Peter Ventzek ,  Sumie Segawa

IPC分类号： C23F1/08 ,  C23C16/50 ,  C23F1/00 ,  C23C16/511 ,  C23C16/00

CPC分类号： H01L21/3145 ,  H01J37/32192 ,  H01J37/3222 ,  H01L21/02247 ,  H01L21/02332 ,  H01L21/318 ,  H01L21/67069 ,  H01L21/68735 ,  H01L21/68742

摘要： A wafer is disposed in a chamber, a plasma generating space is formed in the chamber, plasma processing is performed to the front surface of the processing object while keeping at least the front surface of the processing object in contact with the plasma generating space. The plasma processing is performed with the plasma generating space being kept in contact with at least the peripheral region of the back surface of the processing object.

摘要翻译： 将晶片设置在室中，在室内形成等离子体产生空间，同时至少使处理对象的前表面与等离子体产生空间保持接触，对处理对象的前表面进行等离子体处理。 等离子体处理是在等离子体产生空间与加工对象的后表面的至少周边区域保持接触的情况下进行的。

公开(公告)号：US08384207B2

公开(公告)日：2013-02-26

申请号：US11988012

申请日：2006-08-23

申请人： Hiroyuki Toshima ,  Natsuo Nakamura

发明人： Hiroyuki Toshima ,  Natsuo Nakamura

IPC分类号： H01L23/04 ,  H01L29/40

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/50 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06551

摘要： A semiconductor integrated circuit device (10) which has a layered structure is composed of a plurality of semiconductor layers (L1, L2, L3) in which an integrated circuit is formed on a substrate. Each of the semiconductor layers (L1, L2, L3) has a semiconductor integrated circuit portion (16) that includes the abovementioned integrated circuit on a substrate (11). Each of the semiconductor layers (L1, L2, L3) also has on a substrate at least one unit of through-wiring (17a) for electrically connecting the integrated circuit included in the semiconductor integrated circuit portion (16) to an integrated circuit of another semiconductor layer, and a surrounding insulation portion (18) for surrounding and insulating the through-wiring from the semiconductor integrated circuit portion. A structure formed by the surrounding insulation portion (18) and the through-wiring portion (17) composed of a plurality of units of through-wiring (17a) reduces the resistance of the through-wiring portion and increases the degree of integration of a circuit.

摘要翻译： 具有层叠结构的半导体集成电路器件（10）由在基板上形成集成电路的多个半导体层（L1，L2，L3）构成。 半导体层（L1，L2，L3）中的每一个具有在基板（11）上包括上述集成电路的半导体集成电路部分（16）。 每个半导体层（L1，L2，L3）还在衬底上具有用于将包括在半导体集成电路部分（16）中的集成电路与另一个的集成电路电连接的贯通布线（17a）的至少一个单元 半导体层，以及用于从半导体集成电路部分包围并绝缘贯通布线的环绕绝缘部分（18）。 由周围的绝缘部分（18）和由多个贯通布线（17a）组成的贯通布线部分（17）形成的结构降低了贯通布线部分的电阻并且增加了一个 电路。

公开(公告)号：US07594805B2

公开(公告)日：2009-09-29

申请号：US11193368

申请日：2005-08-01

申请人： Nobuaki Miyakawa ,  Hiroyuki Toshima ,  Natsuo Nakamura ,  Takahiro Kimura

发明人： Nobuaki Miyakawa ,  Hiroyuki Toshima ,  Natsuo Nakamura ,  Takahiro Kimura

IPC分类号： H01L21/56

CPC分类号： H01L21/67092 ,  H01L21/6715 ,  H01L2924/0002 ,  H01L2924/00

摘要： Adhesive injection apparatus, designed to inject an adhesive into gaps between a plurality of layers of flat plate members, includes: a receptacle for holding therein the flat plate members; an evacuation section for evacuating the interior of the receptacle and the gaps between the flat plate members; an adhesive supply section for supplying the adhesive into the receptacle; and a gas introduction section for introducing a gas into the receptacle to produce a pressure difference between the interior of the receptacle and the gaps between the flat plate members, so as to allow the adhesive to be injected from all around the flat plate members into the gaps.

摘要翻译： 粘合剂注射装置，设计用于将粘合剂注入到多个平板构件层之间的间隙中，包括：用于在其中保持平板构件的容器; 用于抽出容器内部和平板构件之间的间隙的抽空部; 用于将粘合剂供应到容器中的粘合剂供应部分; 以及用于将气体引入容器中以在容器内部和平板构件之间的间隙之间产生压力差的气体引入部分，以便允许粘合剂从平板构件的周围注入到 差距

公开(公告)号：US20080184543A1

公开(公告)日：2008-08-07

申请号：US12024445

申请日：2008-02-01

申请人： Takuji Sako ,  Yusaku Kashiwagi ,  Hiroyuki Toshima ,  Kaoru Maekawa

发明人： Takuji Sako ,  Yusaku Kashiwagi ,  Hiroyuki Toshima ,  Kaoru Maekawa

IPC分类号： H01L21/768 ,  H01L21/67

CPC分类号： H01L23/53238 ,  H01J37/32192 ,  H01L21/02074 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76883 ,  H01L21/76886 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device manufacturing method capable of preventing an infliction of damage upon an interlayer insulating film and moisture adsorption thereto due to opening to atmosphere in a process of forming a CuSiN barrier by infiltrating Si into a surface of a copper-containing metal film and nitrifying a Si-infiltrated portion is disclosed.When a semiconductor device is manufactured through the processes of preparing a semiconductor substrate having a copper-containing metal film exposed on a surface thereof; purifying a surface of the copper-containing metal film by using radicals or by using a thermo-chemical method; infiltrating Si into the surface of the copper-containing metal film; and nitrifying a Si-infiltrated portion of the copper-containing metal film by radicals, the purification process, the Si introduction process and the nitrification process are successively performed without breaking a vacuum.

摘要翻译： 一种半导体器件制造方法，其能够防止在通过将Si渗入到含铜金属膜的表面中而形成CuSiN势垒的过程中由于向大气开放而对层间绝缘膜造成的损害和水分吸附，并且硝化 公开了Si渗透部分。 当半导体器件通过制备在其表面上暴露的含铜金属膜的半导体衬底的工艺制造时; 通过使用自由基或使用热化学方法来净化含铜金属膜的表面; 将Si渗入含铜金属膜的表面; 并且通过自由基对含铜金属膜的Si渗透部分进行硝化，在不破坏真空的情况下连续进行净化处理，Si引入工序和硝化处理。

公开(公告)号：US07308395B2

公开(公告)日：2007-12-11

申请号：US10757415

申请日：2004-01-15

申请人： Hisashi Kaneko ,  Motoya Okazaki ,  Hiroyuki Toshima

发明人： Hisashi Kaneko ,  Motoya Okazaki ,  Hiroyuki Toshima

IPC分类号： G06F17/50 ,  G06F9/455 ,  H01L21/66 ,  G01R31/26

CPC分类号： G06F17/5068

摘要： According to an aspect of the present invention, there is provided a simulation circuit pattern evaluation method including: designing an aggregate of simulation circuit patterns, which simulate a circuit pattern of a semiconductor integrated circuit, by combining plural geometrical structure defining parameters respectively having at least two states in such a manner that the respective states appear the same number of times in the respective geometrical structure defining parameters; forming the aggregate of the simulation circuit patterns on a substrate; and evaluating the formed aggregate of the simulation circuit patterns.

摘要翻译： 根据本发明的一个方面，提供了一种仿真电路图案评估方法，包括：通过组合多个几何结构来设计模拟电路图案的集合，模拟电路图案模拟半导体集成电路的电路图案， 两种状态使得各个状态在相应的几何结构定义参数中出现相同的次数; 在基板上形成模拟电路图案的集合体; 并对所形成的仿真电路图案进行评估。

公开(公告)号：US20090114988A1

公开(公告)日：2009-05-07

申请号：US11988012

申请日：2006-08-23

申请人： Hiroyuki Toshima ,  Natsuo Nakamura

发明人： Hiroyuki Toshima ,  Natsuo Nakamura

IPC分类号： H01L29/04 ,  H01L21/18

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/50 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06551

摘要： A semiconductor integrated circuit device (10) which has a layered structure is composed of a plurality of semiconductor layers (L1, L2, L3) in which an integrated circuit is formed on a substrate. Each of the semiconductor layers (L1, L2, L3) has a semiconductor integrated circuit portion (16) that includes the abovementioned integrated circuit on a substrate (11). Each of the semiconductor layers (L1, L2, L3) also has on a substrate at least one unit of through-wiring (17a) for electrically connecting the integrated circuit included in the semiconductor integrated circuit portion (16) to an integrated circuit of another semiconductor layer, and a surrounding insulation portion (18) for surrounding and insulating the through-wiring from the semiconductor integrated circuit portion. A structure formed by the surrounding insulation portion (18) arid the through-wiring portion (17) composed of a plurality of units of through-wiring (17a) reduces the resistance of the through-wiring portion and increases the degree of integration of a circuit.

摘要翻译： 具有层叠结构的半导体集成电路器件（10）由在基板上形成集成电路的多个半导体层（L1，L2，L3）构成。 半导体层（L1，L2，L3）中的每一个具有在基板（11）上包括上述集成电路的半导体集成电路部分（16）。 每个半导体层（L1，L2，L3）还在衬底上具有用于将包括在半导体集成电路部分（16）中的集成电路与另一个的集成电路电连接的贯通布线（17a）的至少一个单元 半导体层，以及用于从半导体集成电路部分包围并绝缘贯通布线的环绕绝缘部分（18）。 由围绕绝缘部分（18）形成的结构以及由多个贯通布线（17a）组成的贯通布线部分（17）形成的结构降低了贯通布线部分的电阻并增加了 电路。