利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

17 条记录 (耗时 0.023 秒)

    Semiconductor integrated circuit device including input circuitry to permit operation of a Bi-CMOS memory with ECL level input signals
    3.
    发明授权
    Semiconductor integrated circuit device including input circuitry to permit operation of a Bi-CMOS memory with ECL level input signals 失效
    半导体集成电路器件包括输入电路，以允许具有ECL电平输入信号的Bi-CMOS存储器的操作

    公开(公告)号：US5457412A

    公开(公告)日：1995-10-10

    申请号：US149935

    申请日：1993-11-10

    申请人： Nobuo Tamba ,  Masanori Odaka ,  Toshiro Hiramoto ,  Masayuki Ohayashi ,  Kayoko Saito

    发明人： Nobuo Tamba ,  Masanori Odaka ,  Toshiro Hiramoto ,  Masayuki Ohayashi ,  Kayoko Saito

    IPC分类号： G11C11/413 ,  H01L21/8249 ,  H01L27/06 ,  H03K19/0175 ,  H03K19/08

    CPC分类号： H03K19/017527

    摘要： A semiconductor integrated circuit device is provided for permitting operation of a CMOS or BiCMOS memory with ECL level input signals, in which operating speed is increased and power consumption is reduced.Input signals of ECL levels are received by an input buffer for amplifying the input signals to an output signal level within a range where differential transistors of the input buffer operate in an unsaturation region. The output signal of the input buffer is supplied to a CMOS circuit or Bi-CMOS circuit which is operated by both an operating voltage having a first-stage smaller absolute value than that of the operating voltage of the input buffer and the ground potential of the circuit. This first stage CMOS or BiCMOS circuit also includes an arrangement to further amplify the received signals to provide further level conversion.Since both the input buffer and the first-stage CMOS or Bi-CMOS circuit perform signal transmission and level conversions, high-speed operation and low power consumption can be achieved by a simple structure.

    摘要翻译： 提供了一种半导体集成电路器件，用于允许具有ECL电平输入信号的CMOS或BiCMOS存储器的操作，其中操作速度增加并且功耗降低。 ECL电平的输入信号由输入缓冲器接收，用于将输入信号放大到输入缓冲器的差分晶体管在不饱和区域中操作的范围内的输出信号电平。 输入缓冲器的输出信号被提供给CMOS电路或Bi-CMOS电路，该CMOS电路或Bi-CMOS电路由具有比输入缓冲器的工作电压的绝对值小的第一级的工作电压和 电路。 该第一级CMOS或BiCMOS电路还包括进一步放大接收信号以提供进一步电平转换的装置。 由于输入缓冲器和第一级CMOS或Bi-CMOS电路都执行信号传输和电平转换，所以可以通过简单的结构实现高速操作和低功耗。

    Semiconductor integrated circuit device forming on a common substrate MISFETs isolated by a field oxide and bipolar transistors isolated by a groove
    7.
    发明授权
    Semiconductor integrated circuit device forming on a common substrate MISFETs isolated by a field oxide and bipolar transistors isolated by a groove 失效
    在公共衬底上形成的半导体集成电路器件通过由沟槽隔离的场氧化物和双极晶体管隔离的MISFET

    公开(公告)号：US5214302A

    公开(公告)日：1993-05-25

    申请号：US807411

    申请日：1991-12-13

    申请人： Akihisa Uchida ,  Keiichi Higeta ,  Nobuo Tamba ,  Masanori Odaka ,  Katsumi Ogiue

    发明人： Akihisa Uchida ,  Keiichi Higeta ,  Nobuo Tamba ,  Masanori Odaka ,  Katsumi Ogiue

    IPC分类号： H01L27/06 ,  H01L27/11 ,  H01L29/732

    CPC分类号： H01L29/7325 ,  H01L27/0623 ,  H01L27/1112

    摘要： A semiconductor integrated circuit device having a structure in which each of the following regions, that is, a first region for forming the base and emitter regions of each of the bipolar transistors, a second region for forming the collector lead-out region of the bipolar transistor, and a third region for forming each of the MISFETs, is projected from the main surface of a semiconductor substrate, whereby it is possible to effect isolation between the MISFETs and between these MISFETs and the bipolar transistors with the same isolation structure and in the same manufacturing step as those for the isolation between the bipolar transistors. In this device, furthermore, the base region of the bipolar transistor is electrically and self-alignedly connected to a base electrode which is formed over the main surface so as to surround the emitter region. The bipolar transistor is characterized as a self-alignment transistor and that the insulating side wall spacers corresponding to the gate and base (emitter) electrodes are formed by a same lever.

    摘要翻译： 一种半导体集成电路器件，具有以下结构，其中以下各个区域，即用于形成每个双极晶体管的基极和发射极区域的第一区域，用于形成双极性的集电极导出区域的第二区域 晶体管和用于形成每个MISFET的第三区域从半导体衬底的主表面突出，由此可以实现MISFET之间以及这些MISFET与具有相同隔离结构的双极晶体管之间的隔离，并且在 与双极晶体管之间的隔离相同的制造步骤。 此外，在该器件中，双极晶体管的基极区域电自自对准地连接到形成在主表面上以围绕发射极区域的基极。 双极晶体管的特征在于自对准晶体管，并且与栅极和基极（发射极）电极对应的绝缘侧壁间隔物由相同的杆形成。

    Variable logic integrated circuit device having connections through switch matrix and top layers for inter-cell connections
    10.
    发明授权
    Variable logic integrated circuit device having connections through switch matrix and top layers for inter-cell connections 失效
    可变逻辑集成电路器件具有通过开关矩阵和顶层连接的单元间连接的连接

    公开(公告)号：US5825203A

    公开(公告)日：1998-10-20

    申请号：US747339

    申请日：1996-11-12

    申请人： Mitsugu Kusunoki ,  Nobuo Tamba

    发明人： Mitsugu Kusunoki ,  Nobuo Tamba

    IPC分类号： H01L21/82 ,  H03K19/177

    CPC分类号： H03K19/17736 ,  H03K19/17792

    摘要： A variable logic integrated circuit device formed on a semiconductor chip comprising variable logic blocks and switch matrices laid out alternately in the X and Y directions in a checkerboard pattern. Above the variable logic blocks is a block interconnection wiring arrangement formed by multiple-layer wiring techniques. The variable logic blocks and switch matrices are wired into circuits respectively by a lower wiring layer in the multiple wiring layer setup of the chip. The block interconnection wiring is formed by an upper wiring layer extending above the variable logic blocks and included in the multiple wiring layer setup. The switch matrices are used to connect the block interconnection lines to one another as well as to the variable logic blocks.

    摘要翻译： 形成在半导体芯片上的可变逻辑集成电路器件，其包括以棋盘图案在X和Y方向交替布置的可变逻辑块和开关矩阵。 可变逻辑块之上是通过多层布线技术形成的块互连布线布置。 可变逻辑块和开关矩阵分别通过芯片的多个布线层设置中的下布线层布线到电路中。 块互连布线由在可变逻辑块之上延伸并包括在多个布线层设置中的上布线层形成。 开关矩阵用于将块互连线彼此连接到可变逻辑块。