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    Variable logic integrated circuit device having connections through switch matrix and top layers for inter-cell connections
    1.
    发明授权
    Variable logic integrated circuit device having connections through switch matrix and top layers for inter-cell connections 失效
    可变逻辑集成电路器件具有通过开关矩阵和顶层连接的单元间连接的连接

    公开(公告)号：US5825203A

    公开(公告)日：1998-10-20

    申请号：US747339

    申请日：1996-11-12

    申请人： Mitsugu Kusunoki ,  Nobuo Tamba

    发明人： Mitsugu Kusunoki ,  Nobuo Tamba

    IPC分类号： H01L21/82 ,  H03K19/177

    CPC分类号： H03K19/17736 ,  H03K19/17792

    摘要： A variable logic integrated circuit device formed on a semiconductor chip comprising variable logic blocks and switch matrices laid out alternately in the X and Y directions in a checkerboard pattern. Above the variable logic blocks is a block interconnection wiring arrangement formed by multiple-layer wiring techniques. The variable logic blocks and switch matrices are wired into circuits respectively by a lower wiring layer in the multiple wiring layer setup of the chip. The block interconnection wiring is formed by an upper wiring layer extending above the variable logic blocks and included in the multiple wiring layer setup. The switch matrices are used to connect the block interconnection lines to one another as well as to the variable logic blocks.

    摘要翻译： 形成在半导体芯片上的可变逻辑集成电路器件，其包括以棋盘图案在X和Y方向交替布置的可变逻辑块和开关矩阵。 可变逻辑块之上是通过多层布线技术形成的块互连布线布置。 可变逻辑块和开关矩阵分别通过芯片的多个布线层设置中的下布线层布线到电路中。 块互连布线由在可变逻辑块之上延伸并包括在多个布线层设置中的上布线层形成。 开关矩阵用于将块互连线彼此连接到可变逻辑块。

    Semiconductor integrated circuit device including input circuitry to permit operation of a Bi-CMOS memory with ECL level input signals
    5.
    发明授权
    Semiconductor integrated circuit device including input circuitry to permit operation of a Bi-CMOS memory with ECL level input signals 失效
    半导体集成电路器件包括输入电路，以允许具有ECL电平输入信号的Bi-CMOS存储器的操作

    公开(公告)号：US5457412A

    公开(公告)日：1995-10-10

    申请号：US149935

    申请日：1993-11-10

    申请人： Nobuo Tamba ,  Masanori Odaka ,  Toshiro Hiramoto ,  Masayuki Ohayashi ,  Kayoko Saito

    发明人： Nobuo Tamba ,  Masanori Odaka ,  Toshiro Hiramoto ,  Masayuki Ohayashi ,  Kayoko Saito

    IPC分类号： G11C11/413 ,  H01L21/8249 ,  H01L27/06 ,  H03K19/0175 ,  H03K19/08

    CPC分类号： H03K19/017527

    摘要： A semiconductor integrated circuit device is provided for permitting operation of a CMOS or BiCMOS memory with ECL level input signals, in which operating speed is increased and power consumption is reduced.Input signals of ECL levels are received by an input buffer for amplifying the input signals to an output signal level within a range where differential transistors of the input buffer operate in an unsaturation region. The output signal of the input buffer is supplied to a CMOS circuit or Bi-CMOS circuit which is operated by both an operating voltage having a first-stage smaller absolute value than that of the operating voltage of the input buffer and the ground potential of the circuit. This first stage CMOS or BiCMOS circuit also includes an arrangement to further amplify the received signals to provide further level conversion.Since both the input buffer and the first-stage CMOS or Bi-CMOS circuit perform signal transmission and level conversions, high-speed operation and low power consumption can be achieved by a simple structure.

    摘要翻译： 提供了一种半导体集成电路器件，用于允许具有ECL电平输入信号的CMOS或BiCMOS存储器的操作，其中操作速度增加并且功耗降低。 ECL电平的输入信号由输入缓冲器接收，用于将输入信号放大到输入缓冲器的差分晶体管在不饱和区域中操作的范围内的输出信号电平。 输入缓冲器的输出信号被提供给CMOS电路或Bi-CMOS电路，该CMOS电路或Bi-CMOS电路由具有比输入缓冲器的工作电压的绝对值小的第一级的工作电压和 电路。 该第一级CMOS或BiCMOS电路还包括进一步放大接收信号以提供进一步电平转换的装置。 由于输入缓冲器和第一级CMOS或Bi-CMOS电路都执行信号传输和电平转换，所以可以通过简单的结构实现高速操作和低功耗。

    Semiconductor memory device
    7.
    再颁专利
    Semiconductor memory device 有权

    公开(公告)号：USRE38545E1

    公开(公告)日：2004-07-06

    申请号：US09636642

    申请日：2000-08-08

    申请人： Toshiro Hiramoto ,  Nobuo Tamba ,  Motoki Kasai

    发明人： Toshiro Hiramoto ,  Nobuo Tamba ,  Motoki Kasai

    IPC分类号： H01L2976

    CPC分类号： G11C11/412 ,  H01L27/1104

    摘要： A semiconductor memory device having a plurality of memory cells each comprising two CMOS inverters cross-coupled to each other and arranged at intersections between a plurality of word lines extending in a column direction and a plurality of complementary data line pairs extending in a row direction; wherein p-channel type load MISFETs of the memory cells arranged in the column direction are formed on the main surface of an n-type well region in the direction in which the word lines extend, the source regions of the p-channel type load MISFETs of the memory cells arranged in the column direction are electrically connected to the n-type well region through conductor layers, and each of the conductor layer is formed independently of the memory cells arranged in the column direction. More specifically, the n-type well regions are fed with a first fixed potential, and the source region of each of the p-channel type load MISFETs is fed with the first fixed potential through the conductor layers which are formed independently.

    Semiconductor memory device
    10.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5854497A

    公开(公告)日：1998-12-29

    申请号：US773312

    申请日：1996-12-24

    申请人： Toshiro Hiramoto ,  Nobuo Tamba ,  Motoki Kasai

    发明人： Toshiro Hiramoto ,  Nobuo Tamba ,  Motoki Kasai

    IPC分类号： G11C11/412 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/76 ,  G11C11/00

    CPC分类号： G11C11/412 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

    摘要： A semiconductor memory device having a plurality of memory cells each comprising two CMOS inverters cross-coupled to each other and arranged at intersections between a plurality of word lines extending in a column direction and a plurality of complementary data line pairs extending in a row direction; wherein p-channel type load MISFETs of the memory cells arranged in the column direction are formed on the main surface of an n-type well region in the direction in which the word lines extend, the source regions of the p-channel type load MISFETs of the memory cells arranged in the column direction are electrically connected to the n-type well region through conductor layers, and each of the conductor layer is formed independently of the memory cells arranged in the column direction.More specifically, the n-type well regions are fed with a first fixed potential, and the source region of each of the p-channel type load MISFETs is fed with the first fixed potential through the conductor layers which are formed independently.

    摘要翻译： 一种半导体存储器件，具有多个存储单元，每个存储单元包括彼此交叉耦合并且布置在沿列方向延伸的多个字线和沿行方向延伸的多个互补数据线对的交点处的两个CMOS反相器; 其中沿着列方向布置的存储单元的p沟道型负载MISFET形成在n型阱区域的字线延伸方向的主表面上，p沟道型负载MISFET的源极区域 沿列方向布置的存储单元通过导体层电连接到n型阱区，并且每个导体层独立于沿列方向排列的存储单元而形成。 更具体地，n型阱区域被馈送有第一固定电位，并且每个p沟道型负载MISFET的源极区域通过独立形成的导体层馈送第一固定电位。