利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

12 条记录 (耗时 0.028 秒)

    THERMALLY CONTROLLED, ANTI-SHOCK APPARATUS FOR AUTOMOTIVE ELECTRONICS
    2.
    发明申请
    THERMALLY CONTROLLED, ANTI-SHOCK APPARATUS FOR AUTOMOTIVE ELECTRONICS 审中-公开
    自动控制，汽车电子防震装置

    公开(公告)号：US20110100666A1

    公开(公告)日：2011-05-05

    申请号：US12611868

    申请日：2009-11-03

    申请人： Albert T. Wu

    发明人： Albert T. Wu

    IPC分类号： H02G3/03 ,  H01B3/00

    CPC分类号： H05K7/20872

    摘要： A thermally controlled, anti-shock apparatus for protecting an automotive electronic device. The apparatus includes a first housing having sidewalls that define an interior cavity. A second housing having a reservoir containing fluid is disposed within the interior cavity of the first housing. A sealed housing for carrying the electronic device is disposed within the fluid in the reservoir of the second housing, wherein the fluid provides buoyancy for keeping the sealed housing at least partially afloat within the reservoir. The sealed housing includes an inner fluid impermeable bag for enclosing the protected electronic device and an outer fluid impermeable bag in which the inner bag and electronic device are disposed. A cooling system condenser includes condenser tubing connected to one or more heat dissipating members that are mounted on a thermally conductive panel using one or more high strength magnets.

    摘要翻译： 一种用于保护汽车电子设备的热控抗冲击装置。 该装置包括具有限定内腔的侧壁的第一壳体。 具有包含流体的储存器的第二壳体设置在第一壳体的内部空腔内。 用于承载电子装置的密封壳体设置在第二壳体的储存器内的流体内，其中流体提供浮力以保持密封壳体至少部分地浮在储存器内。 密封的壳体包括用于封装受保护的电子设备的内部不可渗透的液体袋和其中设置内袋和电子设备的外部不可渗透的袋子。 冷却系统冷凝器包括连接到一个或多个散热构件的冷凝器管，其使用一个或多个高强度磁体安装在导热面板上。

    Method for forming minute openings in semiconductor devices
    3.
    发明授权
    Method for forming minute openings in semiconductor devices 有权
    在半导体器件中形成微小开口的方法

    公开(公告)号：US06274436B1

    公开(公告)日：2001-08-14

    申请号：US09256264

    申请日：1999-02-23

    申请人： Dah-Bin Kao ,  Albert T. Wu ,  Tung-Yi Chan

    发明人： Dah-Bin Kao ,  Albert T. Wu ,  Tung-Yi Chan

    IPC分类号： H01L218247

    CPC分类号： H01L27/11521 ,  G11C16/0416 ,  H01L29/42324

    摘要： A method is disclosed for creating a sub-minimum opening in a semiconductor device, comprising the steps of: a) providing a first layer; b) providing a second layer over said first layer; c) providing a third layer over said second layer; d) providing a photoresist mask over said third layer; e) etching said third layer to form defined structures; f) depositing a fourth layer for forming spacers; g) etching said fourth layer to form said spacers; and h) etching said first layer to form an opening in said first layer. In etching the fourth layer to form the spacers, the third layer is generally etched away to form an opening to the first layer, and, in the following step, an opening (or feature) can be etched on the first layer. Generally speaking, the first and third layers can be of any material and should have similar etching rate; the second and fourth layers can be of any material and should have similar etching rate. However, the material for the first and third layers versus the material for the second and fourth layers should have highly dissimilar etching rates. Materials for these layers include and are not limited to polysilicon, oxide, nitride, and metal.

    摘要翻译： 公开了一种用于在半导体器件中产生次最小开口的方法，包括以下步骤：a）提供第一层; b）在所述第一层上提供第二层; c）在所述第二层上提供第三层; d）在所述第三层上提供光刻胶掩模; e）蚀刻所述第三层以形成限定的结构; f）沉积用于形成间隔物的第四层; g）蚀刻所述第四层以形成所述间隔物; 以及h）蚀刻所述第一层以在所述第一层中形成开口。 在蚀刻第四层以形成间隔物时，通常蚀刻掉第三层以形成到第一层的开口，并且在随后的步骤中，可以在第一层上蚀刻开口（或特征）。 一般来说，第一层和第三层可以是任何材料，并且应该具有相似的蚀刻速率; 第二层和第四层可以是任何材料，并且应该具有相似的蚀刻速率。 然而，第一层和第三层的材料与第二层和第四层的材料应具有高度不同的蚀刻速率。 这些层的材料包括但不限于多晶硅，氧化物，氮化物和金属。

    Electrically programmable memory device employing source side injection
    4.
    发明授权
    Electrically programmable memory device employing source side injection 失效
    采用源极注入的电子可编程存储器件

    公开(公告)号：US4794565A

    公开(公告)日：1988-12-27

    申请号：US907564

    申请日：1986-09-15

    申请人： Albert T. Wu ,  Ping K. Ko ,  Tung-Yi Chan ,  Chenming Hu

    发明人： Albert T. Wu ,  Ping K. Ko ,  Tung-Yi Chan ,  Chenming Hu

    IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  G11C7/00 ,  G11C11/40 ,  H01L29/78

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/7885

    摘要： An electrically programmable and eraseable memory element using source-side hot-electron injection. A semi-conductor substrate of a first conductivity type is provided with a source region and a drain region of opposite conductivity type and a channel region of the first conductivity type extending between the source and drain regions. A control gate overlies the channel region, and a floating gate insulated from the control gate, the source and drain regions and the channel region is located either directly underneath the control gate over the channel region, partially underneath the control gate over the channel region or spaced to the source side of the control gate. A weak gate control region is provided in the device near the source so that a relatively high channel electric field for promoting hot-electron injection is created under the weak gate control region when the device is biased for programming.

    摘要翻译： 使用源侧热电子注入的电可编程和可擦除存储元件。 第一导电类型的半导体衬底设置有具有相反导电类型的源极区域和漏极区域以及在源极和漏极区域之间延伸的第一导电类型的沟道区域。 控制栅极覆盖沟道区域，并且与控制栅极，源极和漏极区域以及沟道区域绝缘的浮置栅极位于通道区域的正下方的控制栅极的下方，部分地位于通道区域的控制栅极下方，或 与控制门的源侧间隔开。 在源极附近的器件中提供弱栅极控制区域，使得当器件偏置编程时，在弱栅极控制区域下产生用于促进热电子注入的较高通道电场。

    CARGO CONTAINER SECURITY SYSTEM
    5.
    发明申请
    CARGO CONTAINER SECURITY SYSTEM 审中-公开
    货物集装箱安全系统

    公开(公告)号：US20120050531A1

    公开(公告)日：2012-03-01

    申请号：US12869594

    申请日：2010-08-26

    申请人： Albert T. Wu

    发明人： Albert T. Wu

    IPC分类号： H04N7/18 ,  G11B23/00 ,  G08B21/00

    CPC分类号： G08B13/08 ,  G08B13/19697

    摘要： A cargo container security system and method, including a cargo container with at least one sensor for detecting an open or closed status of a door on the cargo container and a geographic positioning locator for identifying a location of the cargo container. A control unit, located on the cargo container and operatively connected to the at least one sensor and geographic positioning locator, continuously receives historical data corresponding to at least the status of the cargo container door and location of the cargo container while the cargo container is in transit. The control unit assigns a timestamp to the received historical data, and stores the received historical data and associated timestamp in memory. A central computer system receives and analyzes the stored historical data for any anomalies upon the arrival of the cargo container at a destination. The central computer system generates an alert if an anomaly is identified.

    摘要翻译： 一种货物集装箱安全系统和方法，包括具有用于检测货物集装箱上的门的打开或关闭状态的至少一个传感器的货物集装箱和用于识别货物集装箱的位置的地理定位定位器。 位于货物集装箱上并可操作地连接至至少一个传感器和地理定位定位器的控制单元连续接收与货物集装箱进入货物集装箱门的至少状态和货物集装箱的位置相对应的历史数据 过境 控制单元为所接收的历史数据分配时间戳，并将接收到的历史数据和关联的时间戳存储在存储器中。 中央计算机系统在货物集装箱到达目的地时收到并分析存储的历史数据以查找任何异常情况。 如果识别到异常，中央计算机系统会生成警报。

    Method and apparatus for split gate source side injection flash memory cell and array with dedicated erase gates
    6.
    发明授权
    Method and apparatus for split gate source side injection flash memory cell and array with dedicated erase gates 有权
    用于具有专用擦除栅极的分离栅极源侧注入闪存单元和阵列的方法和装置

    公开(公告)号：US06876031B1

    公开(公告)日：2005-04-05

    申请号：US09256265

    申请日：1999-02-23

    申请人： Dah-Bin Kao ,  Loc B. Hoang ,  Albert T. Wu ,  Tung-Yi Chan

    发明人： Dah-Bin Kao ,  Loc B. Hoang ,  Albert T. Wu ,  Tung-Yi Chan

    IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788

    CPC分类号： H01L27/11521 ,  G11C16/0416 ,  H01L27/115 ,  H01L29/42324

    摘要： A transistor structure having a dedicated erase gate where the transistor can be used as a memory cell is disclosed. The presently preferred embodiment of the transistor comprises a floating gate disposed on a substrate and having a control gate and an erase gate overlapping said floating gate, with drain and source regions doped on the substrate. By providing a dedicated erase gate, the gate oxide underneath the control gate can be made thinner and can have a thickness that is conducive to the scaling of the transistor. The overall cell size of the transistor remains the same and the program and read operation can remain the same. Both the common source and buried bitline architecture can be used, namely twin well or triple well architectures. A memory circuit using the transistors of the present invention is disclosed as well for flash memory circuit applications.

    摘要翻译： 公开了具有专用擦除栅极的晶体管结构，其中晶体管可用作存储单元。 晶体管的当前优选实施例包括设置在衬底上的浮置栅极，并且具有与所述浮置栅极重叠的控制栅极和擦除栅极，掺杂在衬底上的漏极和源极区域。 通过提供专用的擦除栅极，可以使控制栅极下方的栅极氧化物变得更薄，并且可以具有有利于晶体管缩放的厚度。 晶体管的整体单元尺寸保持相同，并且程序和读取操作可以保持不变。 可以使用共同的源和掩埋位线架构，即双阱或三阱架构。 对于闪存电路应用也公开了使用本发明的晶体管的存储电路。

    Semiconductor memory array with buried drain lines and processing methods therefor
    7.
    发明授权
    Semiconductor memory array with buried drain lines and processing methods therefor 失效
    具有埋地漏极线的半导体存储器阵列及其处理方法

    公开(公告)号：US06211547B1

    公开(公告)日：2001-04-03

    申请号：US08976751

    申请日：1997-11-24

    申请人： Dah-Bin Kao ,  Loc B. Hoang ,  Albert T. Wu ,  Tung-Yi Chan

    发明人： Dah-Bin Kao ,  Loc B. Hoang ,  Albert T. Wu ,  Tung-Yi Chan

    IPC分类号： H01L29788

    CPC分类号： H01L27/11521 ,  G11C16/0425 ,  H01L27/115 ,  H01L29/42324

    摘要： A semiconductor memory array and methods therefor is provided herein comprising a substrate; a plurality of memory cell field effect transistors formed on said substrate and being arranged thereon into rows and columns of transistors, each transistor includes a channel region interposed between drain and source regions, and overlaid by a control gate region; a plurality of first diffused elongated regions formed within said substrate that electrically connect in common the drain regions of transistors in respective columns; a plurality of second diffused elongated regions formed within said substrate that electrically connect in common the source regions of transistors in respective columns; and a plurality of elongated conductive line formed over said substrate that electrically connect in common the control gate regions of transistors in respective rows.

    摘要翻译： 本文提供了一种半导体存储器阵列及其方法，包括：衬底; 多个存储单元场效应晶体管，形成在所述基板上并被布置在晶体管的行和列中，每个晶体管包括介于漏极和源极区之间并由控制栅极区重叠的沟道区; 形成在所述基板内的多个第一扩散细长区域，其共同地将各个晶体管的漏极区域电连接; 形成在所述衬底内的多个第二扩散细长区域，其共同地将各个晶体管的源极区域电连接; 以及形成在所述衬底上的多个细长导电线，其共同地电连接相应行中的晶体管的控制栅极区域。

    Memory device and method of operation
    8.
    发明授权
    Memory device and method of operation 失效
    存储器和操作方法

    公开(公告)号：US5903487A

    公开(公告)日：1999-05-11

    申请号：US978157

    申请日：1997-11-25

    申请人： Albert T. Wu ,  Dah-Bin Kao ,  Loc B. Hoang ,  Tung-Yi Chan

    发明人： Albert T. Wu ,  Dah-Bin Kao ,  Loc B. Hoang ,  Tung-Yi Chan

    IPC分类号： G11C11/56 ,  G11C27/00

    CPC分类号： G11C11/5642 ,  G11C11/5621 ,  G11C11/5628 ,  G11C27/005 ,  G11C27/02

    摘要： An analog memory device includes a memory cell transistor and a memory follower transistor that share a common floating gate. The drain of the memory cell transistor is coupled to a first voltage source. The control gate of the memory cell transistor is coupled to a second voltage source. A programming transistor is coupled between the source of the memory cell transistor and a reference voltage. A comparator receives a first input analog signal to be stored in the memory cell transistor and is coupled to the memory follower transistor to receive the signal held on the floating gate. The output of the comparator is coupled to the control gate of the programming transistor to selectively turn it on to store the analog signal in the memory cell transistor.

    摘要翻译： 模拟存储器件包括存储单元晶体管和共享公共浮动栅极的存储器跟随器晶体管。 存储单元晶体管的漏极耦合到第一电压源。 存储单元晶体管的控制栅极耦合到第二电压源。 编程晶体管耦合在存储单元晶体管的源极和参考电压之间。 比较器接收要存储在存储单元晶体管中的第一输入模拟信号，并且耦合到存储器跟随器晶体管以接收保持在浮置栅极上的信号。 比较器的输出耦合到编程晶体管的控制栅极，以选择性地将其导通，以将模拟信号存储在存储单元晶体管中。