公开(公告)号：US20060163630A1

公开(公告)日：2006-07-27

申请号：US11034597

申请日：2005-01-13

申请人： Alessandro Callegari ,  Michael Gribelyuk ,  Dianne Lacey ,  Fenton McFeely ,  Katherine Saenger ,  Sufi Zafar

发明人： Alessandro Callegari ,  Michael Gribelyuk ,  Dianne Lacey ,  Fenton McFeely ,  Katherine Saenger ,  Sufi Zafar

IPC分类号： H01L29/94 ,  H01L29/76 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/4966 ,  C23C14/0036 ,  C23C14/0635 ,  H01L21/28088 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665

摘要： A compound metal comprising TiC which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the TiC compound metal. Furthermore, the TiC metal compound of the present invention is a very efficient oxygen diffusion barrier at 1000° C. allowing very aggressive equivalent oxide thickness (EOT) and inversion layer thickness scaling below 14 Å in a p-metal oxide semiconductor (pMOS) device.

摘要翻译： 提供了包含TiC的复合金属，其是在包括高k电介质和界面层的栅极堆叠上具有约4.75至约5.3，优选约5e的功函数的功函数的热电稳定的p型金属，以及 制造TiC复合金属的方法。 此外，本发明的TiC金属化合物在1000℃下是非常有效的氧扩散阻挡层，允许在p金属氧化物半导体（pMOS）器件中非常有侵蚀性的等效氧化物厚度（EOT）和反型层厚度缩小至低于Å 。

公开(公告)号：US20060138603A1

公开(公告)日：2006-06-29

申请号：US11281032

申请日：2005-11-17

申请人： Cyril Cabral ,  Alessandro Callegari ,  Michael Gribelyuk ,  Paul Jamison ,  Dianne Lacey ,  Fenton McFeely ,  Vijay Narayanan ,  Deborah Neumayer ,  Pushkar Ranade ,  Sufi Zafar

发明人： Cyril Cabral ,  Alessandro Callegari ,  Michael Gribelyuk ,  Paul Jamison ,  Dianne Lacey ,  Fenton McFeely ,  Vijay Narayanan ,  Deborah Neumayer ,  Pushkar Ranade ,  Sufi Zafar

IPC分类号： H01L23/58

CPC分类号： H01L21/02181 ,  C23C16/405 ,  C23C16/56 ,  H01L21/02189 ,  H01L21/02205 ,  H01L21/02271 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/31604 ,  H01L21/823857 ,  H01L27/0805 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating hafnium oxide and/or zirconium oxide films is provided. The methods include providing a mixture of Hf and/or Zr alkoxide dissolved, emulsified or suspended in a liquid; vaporizing at least the alkoxide and depositing the vaporized component at a temperature of greater than 400° C. The resultant film is dense, microcrystalline and is capable of self-passivation when treated in a hydrogen plasma or forming gas anneal.

公开(公告)号：US20060289903A1

公开(公告)日：2006-12-28

申请号：US11513101

申请日：2006-08-30

申请人： Wanda Andreoni ,  Alessandro Callegari ,  Eduard Cartier ,  Alessandro Curioni ,  Christopher D'Emic ,  Evgeni Gousev ,  Michael Gribelyuk ,  Paul Jamison ,  Rajarao Jammy ,  Dianne Lacey ,  Fenton McFeely ,  Vijay Narayanan ,  Carlo Pignedoli ,  Joseph Shepard ,  Sufi Zafar

发明人： Wanda Andreoni ,  Alessandro Callegari ,  Eduard Cartier ,  Alessandro Curioni ,  Christopher D'Emic ,  Evgeni Gousev ,  Michael Gribelyuk ,  Paul Jamison ,  Rajarao Jammy ,  Dianne Lacey ,  Fenton McFeely ,  Vijay Narayanan ,  Carlo Pignedoli ,  Joseph Shepard ,  Sufi Zafar

IPC分类号： H01L31/112 ,  H01L29/80

CPC分类号： H01L21/28176 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78684

摘要： The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2/V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.

摘要翻译： 本发明提供具有高移动性和低界面电荷的栅堆叠结构，以及包括其的半导体器件，即金属氧化物半导体场效应晶体管（MOSFET）。 在半导体器件中，本发明的栅极堆叠结构位于衬底和覆盖栅极导体之间​​。 本发明还提供一种制造本发明的栅叠层结构的方法，其中采用了高温退火工艺（大约800℃）。 在本发明中使用的高温退火提供了一种栅堆叠结构，其具有通过电荷泵浦测量的约8×10 10电荷/ cm 2的界面态密度或 更少，约250cm 2 / Vs或更高的峰迁移率，并且在约6.0×10 12反转电荷/ cm 2处基本上没有迁移率降解， 或更大。

公开(公告)号：US20050280105A1

公开(公告)日：2005-12-22

申请号：US10873733

申请日：2004-06-22

申请人： Wanda Andreoni ,  Alessandro Callegari ,  Eduard Cartier ,  Alessandro Curioni ,  Christopher D'Emic ,  Evengi Gousev ,  Michael Gribelyuk ,  Paul Jamison ,  Rajarao Jammy ,  Dianne Lacey ,  Fenton McFeely ,  Vijay Narayanan ,  Carlo Pignedoli ,  Joseph Shepard ,  Sufi Zafar

发明人： Wanda Andreoni ,  Alessandro Callegari ,  Eduard Cartier ,  Alessandro Curioni ,  Christopher D'Emic ,  Evengi Gousev ,  Michael Gribelyuk ,  Paul Jamison ,  Rajarao Jammy ,  Dianne Lacey ,  Fenton McFeely ,  Vijay Narayanan ,  Carlo Pignedoli ,  Joseph Shepard ,  Sufi Zafar

IPC分类号： H01L21/00 ,  H01L21/28 ,  H01L21/336 ,  H01L21/84 ,  H01L29/49 ,  H01L29/51 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/28176 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78684

摘要： The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2/V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.

摘要翻译： 本发明提供具有高移动性和低界面电荷的栅堆叠结构，以及包括其的半导体器件，即金属氧化物半导体场效应晶体管（MOSFET）。 在半导体器件中，本发明的栅极堆叠结构位于衬底和覆盖栅极导体之间​​。 本发明还提供一种制造本发明的栅叠层结构的方法，其中采用了高温退火工艺（约800℃）。 在本发明中使用的高温退火提供了一种栅堆叠结构，其具有通过电荷泵浦测量的约8×10 10电荷/ cm 2的界面态密度或 更少，约250cm 2 / Vs或更高的峰迁移率，并且在约6.0×10 12反转电荷/ cm 2处基本上不会迁移率降低， 或更大。

公开(公告)号：US20060151846A1

公开(公告)日：2006-07-13

申请号：US11035369

申请日：2005-01-13

申请人： Alessandro Callegari ,  Martin Frank ,  Rajarao Jammy ,  Dianne Lacey ,  Fenton McFeely ,  Sufi Zafar

发明人： Alessandro Callegari ,  Martin Frank ,  Rajarao Jammy ,  Dianne Lacey ,  Fenton McFeely ,  Sufi Zafar

IPC分类号： H01L29/94

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659

摘要： A compound metal comprising HfSiN which is a n-type metal having a workfunction of about 4.0 to about 4.5, preferably about 4.3, eV which is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer. Furthermore, after annealing the stack of HfSiN/high k dielectric/interfacial layer at a high temperature (on the order of about 1000° C.), there is a reduction of the interfacial layer, thus the gate stack produces a very small equivalent oxide thickness (12 Å classical), which cannot be achieved using TaSiN.

公开(公告)号：US20080038905A1

公开(公告)日：2008-02-14

申请号：US11875524

申请日：2007-10-19

申请人： Alessandro Callegari ,  Martin Frank ,  Rajarao Jammy ,  Dianne Lacey ,  Fenton McFeely ,  Sufi Zafar

发明人： Alessandro Callegari ,  Martin Frank ,  Rajarao Jammy ,  Dianne Lacey ,  Fenton McFeely ,  Sufi Zafar

IPC分类号： H01L21/20 ,  C22C16/00

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659

摘要： A compound metal comprising HfSiN which is a n-type metal having a workfunction of about 4.0 to about 4.5, preferably about 4.3, eV which is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer. Furthermore, after annealing the stack of HfSiN/high k dielectric/interfacial layer at a high temperature (on the order of about 1000° C.), there is a reduction of the interfacial layer, thus the gate stack produces a very small equivalent oxide thickness (12 Å classical), which cannot be achieved using TaSiN.

摘要翻译： 包含HfSiN的复合金属，其是具有约4.0至约4.5，优选约4.3的功函数的n型金属，其在包含高k电介质和界面层的栅极堆叠上是热稳定的。 此外，在高温（约1000℃）左右的HfSiN /高k电介质/界面层的堆叠退火之后，界面层的减少，因此栅叠层产生非常小的等效氧化物 厚度（经典），不能用TaSiN实现。

公开(公告)号：US20050250318A1

公开(公告)日：2005-11-10

申请号：US11180384

申请日：2005-07-13

申请人： Vijay Narayanan ,  Fenton McFeely ,  Keith Milkove ,  John Yurkas ,  Matthew Copel ,  Paul Jamison ,  Roy Carruthers ,  Cyril Cabral ,  Edmund Sikorskii ,  Elizabeth Duch ,  Alessandro Callegari ,  Sufi Zafar ,  Kazuhito Nakamura

发明人： Vijay Narayanan ,  Fenton McFeely ,  Keith Milkove ,  John Yurkas ,  Matthew Copel ,  Paul Jamison ,  Roy Carruthers ,  Cyril Cabral ,  Edmund Sikorskii ,  Elizabeth Duch ,  Alessandro Callegari ,  Sufi Zafar ,  Kazuhito Nakamura

IPC分类号： C23C16/34 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/49 ,  H01L29/772 ,  H01L29/78 ,  H01L21/3205 ,  H01L21/31 ,  H01L21/44 ,  H01L21/469 ,  H01L21/4763

CPC分类号： C23C16/34 ,  H01L21/28088 ,  H01L21/823828 ,  H01L29/4966 ,  H01L29/78

摘要： Compounds of Ta and N, potentially including further elements, and with a resistivity below about 20 mΩcm and with the elemental ratio of N to Ta greater than about 0.9 are disclosed for use as gate materials in field effect devices. A representative embodiment of such compounds, TaSiN, is stable at typical CMOS processing temperatures on SiO2 containing dielectric layers and high-k dielectric layers, with a workfunction close to that of n-type Si. Metallic Ta—N compounds are deposited by a chemical vapor deposition method using an alkylimidotris(dialkylamido)Ta species, such as tertiaryamylimidotris(dimethylamido)Ta (TAIMATA), as Ta precursor. The deposition is conformal allowing for flexible introduction of the Ta—N metallic compounds into a CMOS processing flow. Devices processed with TaN or TaSiN show near ideal characteristics.

摘要翻译： 公开了Ta和N的化合物，潜在地包括其它元素，并且电阻率低于约20mOmegacm，并且N与Ta的元素比大于约0.9，用作场效应器件中的栅极材料。 这种化合物的典型实施方案TaSiN在典型的CMOS处理温度下在含有介电层和高k电介质层的SiO 2 2上是稳定的，功函数接近n型Si的功函数。 金属Ta-N化合物通过化学气相沉积方法使用烷基亚氨基三（二烷基酰氨基）Ta种，例如叔戊酰亚胺基三（二甲基酰氨基）Ta（TAIMATA））作为Ta前体沉积。 沉积是共形的，允许将Ta-N金属化合物柔性引入CMOS加工流程。 用TaN或TaSiN处理的器件显示出接近理想的特性。

公开(公告)号：US20050104142A1

公开(公告)日：2005-05-19

申请号：US10712575

申请日：2003-11-13

申请人： Vijav Narayanan ,  Fenton McFeely ,  Keith Milkove ,  John Yurkas ,  Matthew Copel ,  Paul Jamison ,  Roy Carruthers ,  Cyril Cabral ,  Edmund Sikorskii ,  Elizabeth Duch ,  Alessandro Callegari ,  Sufi Zafar ,  Kazuhito Nakamura

发明人： Vijav Narayanan ,  Fenton McFeely ,  Keith Milkove ,  John Yurkas ,  Matthew Copel ,  Paul Jamison ,  Roy Carruthers ,  Cyril Cabral ,  Edmund Sikorskii ,  Elizabeth Duch ,  Alessandro Callegari ,  Sufi Zafar ,  Kazuhito Nakamura

IPC分类号： C23C16/34 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/49 ,  H01L29/772 ,  H01L29/78 ,  H01L29/76

CPC分类号： C23C16/34 ,  H01L21/28088 ,  H01L21/823828 ,  H01L29/4966 ,  H01L29/78

摘要： Compounds of Ta and N, potentially including further elements, and with a resistivity below about 20 mΩcm and with the elemental ratio of N to Ta greater than about 0.9 are disclosed for use as gate materials in field effect devices. A representative embodiment of such compounds, TaSiN, is stable at typical CMOS processing temperatures on SiO2 containing dielectric layers and high-k dielectric layers, with a workfunction close to that of n-type Si. Metallic Ta—N compounds are deposited by a chemical vapor deposition method using an alkylimidotris(dialkylamido)Ta species, such as tertiaryamylimidotris(dimethylamido)Ta (TAIMATA), as Ta precursor. The deposition is conformal allowing for flexible introduction of the Ta—N metallic compounds into a CMOS processing flow. Devices processed with TaN or TaSiN show near ideal characteristics.

摘要翻译： 公开了Ta和N的化合物，潜在地包括其它元素，并且电阻率低于约20mOmegacm，并且N与Ta的元素比大于约0.9，用作场效应器件中的栅极材料。 这种化合物的典型实施方案TaSiN在典型的CMOS处理温度下在含有介电层和高k电介质层的SiO 2 2上是稳定的，功函数接近n型Si的功函数。 金属Ta-N化合物通过化学气相沉积方法使用烷基亚氨基三（二烷基酰氨基）Ta种，例如叔戊酰亚胺基三（二甲基酰氨基）Ta（TAIMATA））作为Ta前体沉积。 沉积是共形的，允许将Ta-N金属化合物柔性引入CMOS加工流程。 用TaN或TaSiN处理的器件显示出接近理想的特性。

公开(公告)号：US20060182886A1

公开(公告)日：2006-08-17

申请号：US11058676

申请日：2005-02-15

申请人： Emmanuel Guidotti ,  Kenji Suzuki ,  Gerrit Leusink ,  Fenton McFeely

发明人： Emmanuel Guidotti ,  Kenji Suzuki ,  Gerrit Leusink ,  Fenton McFeely

IPC分类号： C23C16/00 ,  B05C11/00

CPC分类号： C23C16/4481 ,  C23C16/16 ,  C23C16/4404 ,  C23C16/4405 ,  C23C16/45565

摘要： A method and system for improved delivery of a solid precursor. A chemically inert coating is provided on system components in a precursor delivery line to reduce decomposition of a relatively unstable precursor vapor in the precursor delivery line, thereby allowing increased delivery of the precursor vapor to a processing zone for depositing a layer on a substrate. The solid precursor can, for example, be a ruthenium carbonyl or a rhenium carbonyl. The inert coating can, for example, be a CxFy-containing polymer, such as polytetrafluoroethylene or ethylene-chlorotrifluoroethylene. Other benefits of using an inert coating include easy periodic cleaning of deposits from the precursor delivery line.

摘要翻译： 一种用于改进固体前体递送的方法和系统。 在前体输送管线中的系统组分上提供化学惰性的涂层，以减少前体输送管线中相对不稳定的前体蒸汽的分解，从而允许增加前体蒸气的输送到用于在基底上沉积层的处理区域。 固体前体可以是例如羰基钌或羰基铼。 惰性涂层可以是例如聚四氟乙烯或乙烯 - 三氟氯乙烯的聚合物。 使用惰性涂层的其他优点包括容易地从前体输送管线定期清洁沉积物。

公开(公告)号：US20050199502A1

公开(公告)日：2005-09-15

申请号：US11123117

申请日：2005-05-06

申请人： Panayotis Andricacos ,  Hariklia Deligianni ,  Wilma Horkans ,  Keith Kwietniak ,  Michael Lane ,  Sandra Malhotra ,  Fenton McFeely ,  Conal Murray ,  Kenneth Rodbell ,  Philippe Vereecken

发明人： Panayotis Andricacos ,  Hariklia Deligianni ,  Wilma Horkans ,  Keith Kwietniak ,  Michael Lane ,  Sandra Malhotra ,  Fenton McFeely ,  Conal Murray ,  Kenneth Rodbell ,  Philippe Vereecken

IPC分类号： C25D5/18 ,  C25D7/12 ,  C25D5/02

CPC分类号： C25D5/18 ,  C25D7/12 ,  Y10S428/926 ,  Y10T428/12493 ,  Y10T428/12528 ,  Y10T428/12771 ,  Y10T428/12778 ,  Y10T428/12903

摘要： A conductive material is electroplated onto a platable resistive metal barrier layer(s) employing a plating bath optionally comprising a super filling additive and a suppressor, and by changing the current or voltage as a function of the area of plated metal. A structure is also provided that comprises a substrate, a platable metal barrier layer(s) located on the substrate and a relatively continuous uniform electroplated layer of a conductive material located on the platable resistive metal barrier layer.

摘要翻译： 导电材料电镀在可镀敷的电阻金属阻挡层上，该层使用任选地包含超填充添加剂和抑制剂的电镀槽，并且通过改变作为电镀金属面积的函数的电流或电压。 还提供了一种结构，其包括衬底，位于衬底上的可镀金属阻挡层和位于可镀电阻金属阻挡层上的导电材料的相对连续的均匀电镀层。