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19 条记录 (耗时 0.018 秒)

    Simultaneous multiple silicon on insulator (SOI) wafer production
    1.
    发明授权
    Simultaneous multiple silicon on insulator (SOI) wafer production 有权
    同时多个绝缘体上硅（SOI）晶圆生产

    公开(公告)号：US06326285B1

    公开(公告)日：2001-12-04

    申请号：US09511165

    申请日：2000-02-24

    申请人： Alex A. Behfar ,  Kris V. Srikrishnan

    发明人： Alex A. Behfar ,  Kris V. Srikrishnan

    IPC分类号： H01L2130

    CPC分类号： H01L21/76254

    摘要： A method of forming multiple SOI wafers from a plurality of individual wafers each having a first side and a second side. The method includes forming an oxide surface on the first side on each of the plurality of individual wafers and forming a hydrogen rich region at a preselected depth on the second side on each of the plurality of individual wafers. The wafers are then bonded into a stacked configuration and heat treated to fracture the wafers at the hydrogen rich regions. This fracture forms at least two SOI wafers.

    摘要翻译： 一种从具有第一侧和第二面的多个单独晶片形成多个SOI晶片的方法。 该方法包括在多个单独晶片中的每一个上的第一侧上形成氧化物表面，并且在多个单个晶片中的每一个晶片上在第二侧的预选深度处形成富氢区域。 然后将晶片结合成堆叠构造并进行热处理以在富氢区域处断裂晶片。 该断裂形成至少两个SOI晶片。

    Method of making corrosion resistant, low resistivity copper for interconnect metal lines
    6.
    发明授权
    Method of making corrosion resistant, low resistivity copper for interconnect metal lines 失效
    用于互连金属线的耐腐蚀性，低电阻率铜的方法

    公开(公告)号：US5420069A

    公开(公告)日：1995-05-30

    申请号：US999245

    申请日：1992-12-31

    申请人： Rajiv V. Joshi ,  Manu J. Tejwani ,  Kris V. Srikrishnan

    发明人： Rajiv V. Joshi ,  Manu J. Tejwani ,  Kris V. Srikrishnan

    IPC分类号： H01L21/768 ,  H01L23/498 ,  H01L23/532 ,  H01L21/44

    CPC分类号： H01L21/76852 ,  H01L21/76838 ,  H01L21/76849 ,  H01L23/49866 ,  H01L23/53233 ,  H01L2924/0002

    摘要： The fabrication and use of corrosion resistant Cu/Cu(x)Ge(y) alloy or Cu/Cu.sub.3 Ge phase bilayer interconnect metal lines is disclosed. A solid state, selective process of forming a Cu.sub.3 Ge phase or Cu(x)Ge(y) alloy by reacting GeH.sub.4 gas with Cu surface at low pressure in CVD reactor at temperatures of 200.degree.-450.degree. C. is described. Corrosion resistant semiconductor devices and packaging interconnects where corrosion of copper interconnects was a problem, is now made possible by the Cu/Cu.sub.3 Ge phase or Cu.sub.x Ge.sub.y alloy bilayer of the present invention. A structure where copper vias are completely or partially converted to Cu.sub.3 Ge or Cu.sub.x Ge.sub.y is presented. Also, dissimilar metals like Al--Cu can be connected by Cu.sub.3 Ge phase or Cu.sub.x Ge.sub.y alloy filled vias to improve electromigration performance.

    摘要翻译： 公开了耐蚀Cu / Cu（x）Ge（y）合金或Cu / Cu3Ge相双层互连金属线的制造和使用。 描述了在200-450℃的温度下在CVD反应器中使GeH 4气体与Cu表面在低压下反应形成Cu 3 Ge相或Cu（x）Ge（y）合金的固态选择性过程。 通过本发明的Cu / Cu3Ge相或CuxGey合金双层，现在可以实现铜互连的腐蚀问题的耐腐蚀半导体器件和封装互连。 提出了铜通孔完全或部分转化为Cu3Ge或CuxGey的结构。 此外，不同的金属如Al-Cu可以通过Cu3Ge相或CuxGey合金填充的通孔连接，以提高电迁移性能。

    Smart-cut process for the production of thin semiconductor material films
    10.
    发明授权
    Smart-cut process for the production of thin semiconductor material films 失效
    用于生产薄半导体材料薄膜的智能切割工艺

    公开(公告)号：US5882987A

    公开(公告)日：1999-03-16

    申请号：US920117

    申请日：1997-08-26

    申请人： Kris V. Srikrishnan

    发明人： Kris V. Srikrishnan

    IPC分类号： H01L21/20 ,  H01L21/02 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L21/30

    CPC分类号： H01L21/76254 ,  H01L21/76251 ,  Y10S148/05 ,  Y10S438/977

    摘要： A process applicable to the production of monocrystalline films improves on the Smart-Cut.RTM. process by using an etch stop layer in conjunction with the Smart-Cut.RTM. process. Because of the etch stop layer, no chemical-mechanical polishing (CMP) is required after fabrication. Thus, the thickness and smoothness of the device layer in the fabricated silicon on insulator (SOI) substrate is determined by the uniformity and smoothness of the deposited layers and wet etch selectivity, as opposed to the CMP parameters. Therefore, the smoothness and uniformity of the device layer are improved.

    摘要翻译： 通过使用与Smart-Cut TM工艺结合的蚀刻停止层，适用于单晶膜生产的工艺在Smart-Cut TM工艺上得到改进。 由于蚀刻停止层，制造后不需要化学机械抛光（CMP）。 因此，与CMP参数相反，制造的绝缘体上硅（SOI）衬底中的器件层的厚度和平滑度由沉积层的均匀性和平滑度以及湿蚀刻选择性决定。 因此，改善了器件层的平滑度和均匀性。