公开(公告)号：US20060261876A1

公开(公告)日：2006-11-23

申请号：US11412338

申请日：2006-04-27

申请人： Anant Agarwal ,  Sumithra Krishnaswami ,  James Richmond

发明人： Anant Agarwal ,  Sumithra Krishnaswami ,  James Richmond

IPC分类号： H03K17/687

CPC分类号： H01L29/66068 ,  H01L21/8213 ,  H01L27/0825 ,  H01L29/1608 ,  H01L31/028 ,  H01L31/0304 ,  H01L31/11 ,  H01L31/1113 ,  H01L31/167 ,  H03K17/615 ,  H03K17/79 ,  H03K17/7955 ,  Y10T307/773

摘要： An electronic circuit includes a primary wide bandgap bipolar power switching device configured to supply a load current in response to a control signal applied to a control terminal thereof, and a driver device configured to generate the control signal. At least one of the primary switching device or the driver device may include an optically triggered switching device. A discrete wide bandgap semiconductor device includes a primary bipolar device stage configured to switch between a conducting state and a nonconducting state upon application of a control current, and a bipolar driver stage configured to generate the control current and to supply the control current to the primary bipolar device stage. At least one of the primary bipolar device stage and the bipolar driver stage may include an optically triggered wide bandgap switching device.

摘要翻译： 电子电路包括主宽带隙双极型功率开关装置，其被配置为响应于施加到其控制端的控制信号而提供负载电流;以及驱动器装置，被配置为产生控制信号。 主开关装置或驱动器装置中的至少一个可以包括光学触发的开关装置。 分立的宽带隙半导体器件包括主要双极器件级，其被配置为在施加控制电流时在导通状态和非导通状态之间切换;双极性驱动器级，被配置为产生控制电流并将控制电流提供给初级 双极器件阶段。 主要双极器件级和双极驱动器级中的至少一个可以包括光学触发的宽带隙开关器件。

公开(公告)号：US20070235757A1

公开(公告)日：2007-10-11

申请号：US11229474

申请日：2005-09-16

申请人： Anant Agarwal ,  Sumithra Krishnaswami ,  Sei-Hyung Ryu ,  Edward Hurt

发明人： Anant Agarwal ,  Sumithra Krishnaswami ,  Sei-Hyung Ryu ,  Edward Hurt

IPC分类号： H01L31/00

CPC分类号： H01L29/66068 ,  H01L29/0804 ,  H01L29/1004 ,  H01L29/1608 ,  H01L29/732

摘要： Bipolar junction transistors (BJTs) are provided including silicon carbide (SiC) substrates. An epitaxial SiC base region is provided on the SiC substrate. The epitaxial SiC base region has a first conductivity type. An epitaxial SiC emitter region is also provided on the SiC substrate. The epitaxial SiC emitter region has a second conductivity type, different from the first conductivity type. The epitaxial SiC emitter region has first and second portions. The first portion is provided on the SiC substrate and the second portion is provided on the first portion. The second portion has a higher carrier concentration than the first portion. Related methods of fabricating BJTs are also provided herein.

摘要翻译： 提供双极结晶体管（BJT），包括碳化硅（SiC）衬底。 在SiC衬底上设置外延SiC基区。 外延SiC基区具有第一导电类型。 外延SiC发射极区也设置在SiC衬底上。 外延SiC发射极区域具有不同于第一导电类型的第二导电类型。 外延SiC发射极区域具有第一和第二部分。 第一部分设置在SiC衬底上，第二部分设置在第一部分上。 第二部分具有比第一部分更高的载流子浓度。 本文还提供了制造BJT的相关方法。

公开(公告)号：US20070145378A1

公开(公告)日：2007-06-28

申请号：US11315672

申请日：2005-12-22

申请人： Anant Agarwal ,  Sumithra Krishnaswami ,  Sei-Hyung Ryu ,  D. Capell

发明人： Anant Agarwal ,  Sumithra Krishnaswami ,  Sei-Hyung Ryu ,  D. Capell

IPC分类号： H01L31/0312

CPC分类号： H01L29/1608 ,  H01L29/1004 ,  H01L29/7325

摘要： A bipolar junction transistor (BJT) includes a silicon carbide (SiC) collector layer of first conductivity type, an epitaxial silicon carbide base layer of second conductivity type on the silicon carbide collector layer, and an epitaxial silicon carbide emitter mesa of the first conductivity type on the epitaxial silicon carbide base layer. An epitaxial silicon carbide passivation layer of the first conductivity type is provided on at least a portion of the epitaxial silicon carbide base layer outside the silicon carbide emitter mesa. The epitaxial silicon carbide passivation layer can be configured to fully deplete at zero device bias. Related fabrication methods also are disclosed.

摘要翻译： 双极结型晶体管（BJT）包括第一导电类型的碳化硅（SiC）集电极层，在碳化硅集电极层上的第二导电类型的外延碳化硅基底层和第一导电类型的外延碳化硅发射极台面 在外延碳化硅基底层上。 第一导电类型的外延碳化硅钝化层设置在碳化硅发射极台面外部的外延碳化硅基底层的至少一部分上。 外延碳化硅钝化层可以被配置为在零器件偏置下完全耗尽。 还公开了相关的制造方法。

公开(公告)号：US09984894B2

公开(公告)日：2018-05-29

申请号：US13196994

申请日：2011-08-03

申请人： Sarit Dhar ,  Sei-Hyung Ryu ,  Anant Agarwal ,  John Robert Williams

发明人： Sarit Dhar ,  Sei-Hyung Ryu ,  Anant Agarwal ,  John Robert Williams

IPC分类号： H01L21/336 ,  H01L21/3115 ,  H01L21/04 ,  H01L29/40 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/16 ,  H01L29/08

CPC分类号： H01L21/3115 ,  H01L21/049 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/408 ,  H01L29/51 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7802

摘要： Methods of forming a semiconductor structure include providing an insulation layer on a semiconductor layer and diffusing cesium ions into the insulation layer from a cesium ion source outside the insulation layer. A MOSFET including an insulation layer treated with cesium ions may exhibit increased inversion layer mobility.

公开(公告)号：US09306004B2

公开(公告)日：2016-04-05

申请号：US13108366

申请日：2011-05-16

申请人： Qingchun Zhang ,  Craig Capell ,  Anant Agarwal ,  Sei-Hyung Ryu

发明人： Qingchun Zhang ,  Craig Capell ,  Anant Agarwal ,  Sei-Hyung Ryu

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/36 ,  H01L29/732 ,  H01L29/739 ,  H01L29/74 ,  H01L29/78 ,  H01L29/861 ,  H01L29/16

摘要： A negative bevel edge termination for a Silicon Carbide (SiC) semiconductor device is disclosed. In one embodiment, the negative bevel edge termination includes multiple steps that approximate a smooth negative bevel edge termination at a desired slope. More specifically, in one embodiment, the negative bevel edge termination includes at least five steps, at least ten steps, or at least 15 steps. The desired slope is, in one embodiment, less than or equal to fifteen degrees. In one embodiment, the negative bevel edge termination results in a blocking voltage for the semiconductor device of at least 10 kilovolts (kV) or at least 12 kV. The semiconductor device is preferably, but not necessarily, a thyristor such as a power thyristor, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), a U-channel Metal-Oxide-Semiconductor Field Effect Transistor (UMOSFET), or a PIN diode.

公开(公告)号：US09009660B1

公开(公告)日：2015-04-14

申请号：US11564723

申请日：2006-11-29

申请人： Patrick Robert Griffin ,  Walter Lee ,  Anant Agarwal ,  David Wentzlaff

发明人： Patrick Robert Griffin ,  Walter Lee ,  Anant Agarwal ,  David Wentzlaff

IPC分类号： G06F9/44 ,  G06F9/45 ,  G06F9/48

CPC分类号： G06F8/445 ,  G06F8/30 ,  G06F8/314 ,  G06F8/41 ,  G06F8/427 ,  G06F8/437 ,  G06F8/447 ,  G06F8/451 ,  G06F8/453 ,  G06F9/48 ,  G06F9/546 ,  G06F2209/548

摘要： Programming in a multiprocessor environment includes accepting a program specification that defines a plurality of processing modules and one or more channels for sending data between ports of the modules, mapping each of the processing modules to run on a set of one or more processing engines of a network of interconnected processing engines, and for at least some of the channels, assigning one or more elements of one or more processing engines in the network to the channel for sending data between respective processing modules.

摘要翻译： 在多处理器环境中的编程包括接受定义多个处理模块的程序规范和用于在模块的端口之间发送数据的一个或多个通道，将每个处理模块映射到一组一个或多个处理引擎上 互联处理引擎的网络，以及至少一些信道，将网络中的一个或多个处理引擎的一个或多个元素分配给用于在各个处理模块之间发送数据的信道。

公开(公告)号：US08546874B2

公开(公告)日：2013-10-01

申请号：US13267966

申请日：2011-10-07

申请人： Allen Hefner ,  Sei-Hyung Ryu ,  Anant Agarwal

发明人： Allen Hefner ,  Sei-Hyung Ryu ,  Anant Agarwal

IPC分类号： H01L29/76

CPC分类号： H01L29/7803 ,  H01L21/0465 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7828 ,  H01L29/861

摘要： A semiconductor device includes a drift layer and a body region that forms a p-n junction with the drift layer. A contactor region is in the body region, and a shunt channel region extends through the body region from the contactor region to the drift layer. The shunt channel region has a length, thickness and doping concentration selected such that: 1) the shunt channel region is fully depleted when zero voltage is applied across the first and second terminals, 2) the shunt channel becomes conductive at a voltages less than the built-in potential of the drift layer to body region p-n junction, and/or 3) the shunt channel is not conductive for voltages that reverse bias the p-n junction between the drift region and the body region.

摘要翻译： 半导体器件包括漂移层和与漂移层形成p-n结的体区。 接触器区域在体区域中，并且分流通道区域从接触器区域延伸穿过体区域到漂移层。 分流沟道区域具有选择的长度，厚度和掺杂浓度，使得：1）当跨越第一和第二端子施加零电压时，并联沟道区域完全耗尽，2）并联沟道在小于 内部电位漂移层到体区pn结，和/或3）并联通道对于反向偏置漂移区域和体区之间的pn结的电压是不导通的。

公开(公告)号：US20130062723A1

公开(公告)日：2013-03-14

申请号：US13229749

申请日：2011-09-11

申请人： Jason Patrick Henning ,  Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant Agarwal ,  John Williams Palmour ,  Scott Allen

发明人： Jason Patrick Henning ,  Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant Agarwal ,  John Williams Palmour ,  Scott Allen

IPC分类号： H01L29/872

CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/1608 ,  H01L29/8611 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/00 ,  H01L2224/05552

摘要： The present disclosure generally relates to a Schottky diode that has a substrate, a drift layer provided over the substrate, and a Schottky layer provided over an active region of the drift layer. The metal for the Schottky layer and the semiconductor material for the drift layer are selected to provide a low barrier height Schottky junction between the drift layer and the Schottky layer.

公开(公告)号：US20130062619A1

公开(公告)日：2013-03-14

申请号：US13229750

申请日：2011-09-11

申请人： Jason Patrick Henning ,  Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant Agarwal ,  John Williams Palmour ,  Scott Allen

发明人： Jason Patrick Henning ,  Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant Agarwal ,  John Williams Palmour ,  Scott Allen

IPC分类号： H01L29/872

CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/8611 ,  H01L2224/04042 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/00 ,  H01L2224/05552

摘要： Elements of an edge termination structure, such as multiple concentric guard rings, are effectively doped regions in a drift layer. To increase the depth of these doped regions, individual recesses may be formed in a surface of the drift layer where the elements of the edge termination structure are to be formed. Once the recesses are formed in the drift layer, these areas about and at the bottom of the recesses are doped to form the respective edge termination elements.

摘要翻译： 边缘终端结构的元件，例如多个同心保护环，是漂移层中的有效掺杂区域。 为了增加这些掺杂区域的深度，可以在要形成边缘终端结构的元件的漂移层的表面中形成各自的凹部。 一旦凹陷形成在漂移层中，凹槽周围和底部的这些区域被掺杂以形成相应的边缘终端元件。

公开(公告)号：US20120292636A1

公开(公告)日：2012-11-22

申请号：US13108366

申请日：2011-05-16

申请人： Qingchun Zhang ,  Craig Capell ,  Anant Agarwal ,  Sei-Hyung Ryu

发明人： Qingchun Zhang ,  Craig Capell ,  Anant Agarwal ,  Sei-Hyung Ryu

IPC分类号： H01L29/161

CPC分类号： H01L29/7813 ,  H01L21/0465 ,  H01L29/0615 ,  H01L29/0661 ,  H01L29/1004 ,  H01L29/1016 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/732 ,  H01L29/7397 ,  H01L29/74 ,  H01L29/861

摘要： A negative bevel edge termination for a Silicon Carbide (SiC) semiconductor device is disclosed. In one embodiment, the negative bevel edge termination includes multiple steps that approximate a smooth negative bevel edge termination at a desired slope. More specifically, in one embodiment, the negative bevel edge termination includes at least five steps, at least ten steps, or at least 15 steps. The desired slope is, in one embodiment, less than or equal to fifteen degrees. In one embodiment, the negative bevel edge termination results in a blocking voltage for the semiconductor device of at least 10 kilovolts (kV) or at least 12 kV. The semiconductor device is preferably, but not necessarily, a thyristor such as a power thyristor, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), a U-channel Metal-Oxide-Semiconductor Field Effect Transistor (UMOSFET), or a PIN diode.

摘要翻译： 公开了一种用于碳化硅（SiC）半导体器件的负斜面边缘终端。 在一个实施例中，负斜边缘终端包括以期望的斜率近似平滑负斜面边缘终止的多个步骤。 更具体地，在一个实施例中，负斜边缘终止包括至少五个步骤，至少十个步骤或至少15个步骤。 在一个实施例中，期望的斜率小于或等于十五度。 在一个实施例中，负斜边缘终止导致半导体器件的阻挡电压为至少10千伏（kV）或至少12kV。 半导体器件优选但不一定是晶闸管，例如功率晶闸管，双极结晶体管（BJT），绝缘栅双极晶体管（IGBT），U沟道金属氧化物半导体场效应晶体管（UMOSFET） 或PIN二极管。