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公开(公告)号：US20140029210A1
公开(公告)日：2014-01-30
申请号：US13561868
申请日：2012-07-30
CPC分类号： H01L23/3121 , H01L21/4853 , H01L21/561 , H01L23/3735 , H01L23/49816 , H01L23/49833 , H01L23/49894 , H01L23/5389 , H01L23/564 , H01L24/19 , H01L24/20 , H01L24/24 , H01L2224/12105 , H01L2224/13022 , H01L2224/131 , H01L2224/24137 , H01L2224/291 , H01L2224/2929 , H01L2224/293 , H01L2224/32225 , H01L2224/73267 , H01L2224/83192 , H01L2224/83855 , H01L2224/92144 , H01L2224/9222 , H01L2224/97 , H01L2924/12042 , H01L2924/15787 , H01L2924/181 , H01L2224/83 , H01L2924/00014 , H01L2924/014 , H01L2924/00
摘要： A surface-mount package structure for reducing the ingress of moisture and gases thereto is disclosed. The surface-mount structure includes a sub-module having a dielectric layer, semiconductor devices attached to the dielectric layer, a first level interconnect structure electrically coupled to the semiconductor devices, and a second level I/O connection electrically coupled to the first level interconnect and formed on the dielectric layer, with the second level I/O connection configured to connect the sub-module to an external circuit. The semiconductor devices of the sub-module are attached to a substrate structure, with a dielectric material positioned between the dielectric layer and the substrate structure to fill in gaps in the surface-mount structure. A diffusion barrier layer is applied over the sub-module, adjacent the first and second level I/O connections, and extends down to the substrate structure to reduce the ingress of moisture and gases from a surrounding environment into the surface-mount structure.
摘要翻译： 公开了一种用于减少水分和气体进入的表面贴装封装结构。 表面安装结构包括具有电介质层的子模块，附着到电介质层的半导体器件，电耦合到半导体器件的第一级互连结构以及电耦合到第一级互连的第二级I / O连接 并形成在电介质层上，其中第二级I / O连接被配置为将子模块连接到外部电路。 子模块的半导体器件附接到衬底结构，其中介电材料位于电介质层和衬底结构之间以填充表面安装结构中的间隙。 扩散阻挡层施加在子模块上，邻近第一和第二级I / O连接，并向下延伸到衬底结构，以减少水分和气体从周围环境进入表面安装结构。
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公开(公告)号：US09299630B2
公开(公告)日：2016-03-29
申请号：US13561868
申请日：2012-07-30
IPC分类号： H01L23/02 , H01L23/31 , H01L23/538 , H01L23/373 , H01L23/498 , H01L21/48 , H01L23/00 , H01L21/56
CPC分类号： H01L23/3121 , H01L21/4853 , H01L21/561 , H01L23/3735 , H01L23/49816 , H01L23/49833 , H01L23/49894 , H01L23/5389 , H01L23/564 , H01L24/19 , H01L24/20 , H01L24/24 , H01L2224/12105 , H01L2224/13022 , H01L2224/131 , H01L2224/24137 , H01L2224/291 , H01L2224/2929 , H01L2224/293 , H01L2224/32225 , H01L2224/73267 , H01L2224/83192 , H01L2224/83855 , H01L2224/92144 , H01L2224/9222 , H01L2224/97 , H01L2924/12042 , H01L2924/15787 , H01L2924/181 , H01L2224/83 , H01L2924/00014 , H01L2924/014 , H01L2924/00
摘要： A surface-mount package structure for reducing the ingress of moisture and gases thereto is disclosed. The surface-mount structure includes a sub-module having a dielectric layer, semiconductor devices attached to the dielectric layer, a first level interconnect structure electrically coupled to the semiconductor devices, and a second level I/O connection electrically coupled to the first level interconnect and formed on the dielectric layer, with the second level I/O connection configured to connect the sub-module to an external circuit. The semiconductor devices of the sub-module are attached to a substrate structure, with a dielectric material positioned between the dielectric layer and the substrate structure to fill in gaps in the surface-mount structure. A diffusion barrier layer is applied over the sub-module, adjacent the first and second level I/O connections, and extends down to the substrate structure to reduce the ingress of moisture and gases from a surrounding environment into the surface-mount structure.
摘要翻译： 公开了一种用于减少水分和气体进入的表面贴装封装结构。 表面安装结构包括具有电介质层的子模块，附着到电介质层的半导体器件，电耦合到半导体器件的第一级互连结构以及电耦合到第一级互连的第二级I / O连接 并形成在电介质层上，其中第二级I / O连接被配置为将子模块连接到外部电路。 子模块的半导体器件附接到衬底结构，其中介电材料位于电介质层和衬底结构之间以填充表面安装结构中的间隙。 扩散阻挡层施加在子模块上，邻近第一和第二级I / O连接，并向下延伸到衬底结构，以减少水分和气体从周围环境进入表面安装结构。
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公开(公告)号：US08941208B2
公开(公告)日：2015-01-27
申请号：US13561811
申请日：2012-07-30
IPC分类号： H01L21/70
CPC分类号： H01L23/49838 , H01L21/4853 , H01L21/56 , H01L21/561 , H01L21/563 , H01L23/3128 , H01L23/3142 , H01L23/3178 , H01L23/3735 , H01L23/49816 , H01L23/49833 , H01L23/49894 , H01L23/5389 , H01L24/24 , H01L24/29 , H01L24/82 , H01L24/83 , H01L24/95 , H01L25/072 , H01L2224/04105 , H01L2224/24137 , H01L2224/29339 , H01L2224/32225 , H01L2224/73267 , H01L2224/83192 , H01L2224/8384 , H01L2224/92144 , H01L2924/0781 , H01L2924/12042 , H01L2924/15311 , H01L2924/15313 , H01L2924/15787 , H01L2924/181 , H01L2924/3511 , H01L2924/00014 , H01L2924/00
摘要： A surface mount packaging structure that yields improved thermo-mechanical reliability and more robust second-level package interconnections is disclosed. The surface mount packaging structure includes a sub-module having a dielectric layer, semiconductor devices attached to the dielectric layer, a first level metal interconnect structure electrically coupled to the semiconductor devices, and a second level I/O connection electrically coupled to the first level interconnect and formed on the dielectric layer on a side opposite the semiconductor devices, with the second level I/O connection configured to connect the sub-module to an external circuit. The semiconductor devices of the sub-module are attached to the first surface of a multi-layer substrate structure, with a dielectric material positioned between the dielectric layer and the multi-layer substrate structure to fill in gaps in the surface-mount structure and provide additional structural integrity thereto.
摘要翻译： 公开了一种表面贴装封装结构，其提供了改善的热机械可靠性和更坚固的二级封装互连。 表面贴装封装结构包括具有电介质层的子模块，附着到电介质层的半导体器件，电耦合到半导体器件的第一级金属互连结构以及电耦合到第一级的第二级I / O连接 互连并形成在与半导体器件相对的一侧的电介质层上，其中第二级I / O连接被配置为将子模块连接到外部电路。 子模块的半导体器件附接到多层衬底结构的第一表面，其中介电材料位于电介质层和多层衬底结构之间以填充表面安装结构中的间隙，并提供 额外的结构完整性。
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公开(公告)号：US20140029234A1
公开(公告)日：2014-01-30
申请号：US13561811
申请日：2012-07-30
CPC分类号： H01L23/49838 , H01L21/4853 , H01L21/56 , H01L21/561 , H01L21/563 , H01L23/3128 , H01L23/3142 , H01L23/3178 , H01L23/3735 , H01L23/49816 , H01L23/49833 , H01L23/49894 , H01L23/5389 , H01L24/24 , H01L24/29 , H01L24/82 , H01L24/83 , H01L24/95 , H01L25/072 , H01L2224/04105 , H01L2224/24137 , H01L2224/29339 , H01L2224/32225 , H01L2224/73267 , H01L2224/83192 , H01L2224/8384 , H01L2224/92144 , H01L2924/0781 , H01L2924/12042 , H01L2924/15311 , H01L2924/15313 , H01L2924/15787 , H01L2924/181 , H01L2924/3511 , H01L2924/00014 , H01L2924/00
摘要： A surface mount packaging structure that yields improved thermo-mechanical reliability and more robust second-level package interconnections is disclosed. The surface mount packaging structure includes a sub-module having a dielectric layer, semiconductor devices attached to the dielectric layer, a first level metal interconnect structure electrically coupled to the semiconductor devices, and a second level I/O connection electrically coupled to the first level interconnect and formed on the dielectric layer on a side opposite the semiconductor devices, with the second level I/O connection configured to connect the sub-module to an external circuit. The semiconductor devices of the sub-module are attached to the first surface of a multi-layer substrate structure, with a dielectric material positioned between the dielectric layer and the multi-layer substrate structure to fill in gaps in the surface-mount structure and provide additional structural integrity thereto.
摘要翻译： 公开了一种表面贴装封装结构，其提供了改善的热机械可靠性和更坚固的二级封装互连。 表面贴装封装结构包括具有电介质层的子模块，附着到电介质层的半导体器件，电耦合到半导体器件的第一级金属互连结构以及电耦合到第一级的第二级I / O连接 互连并形成在与半导体器件相对的一侧的电介质层上，其中第二级I / O连接被配置为将子模块连接到外部电路。 子模块的半导体器件附接到多层衬底结构的第一表面，其中介电材料位于电介质层和多层衬底结构之间以填充表面安装结构中的间隙，并提供 额外的结构完整性。
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5.发明授权公开(公告)号：US09066443B2
公开(公告)日：2015-06-23
申请号：US13231547
申请日：2011-09-13
CPC分类号： H05K1/189 , H01L25/0753 , H01L27/15 , H01L33/005 , H01L33/60 , H01L33/62 , H01L33/64 , H01L33/642 , H01L33/647 , H01L2224/24 , H01L2933/0066 , H01L2933/0075 , H05K1/021 , H05K2201/10106
摘要： A system and method for packaging light emitting semiconductors (LESs) is disclosed. An LES device is provided that includes a heatsink and an array of LES chips mounted on the heatsink and electrically connected thereto, with each LES chip comprising connection pads and a light emitting area configured to emit light therefrom responsive to a received electrical power. The LES device also includes a flexible interconnect structure positioned on and electrically connected to each LES chip to provide for controlLES operation of the array of LES chips, with the flexible interconnect structure further including a flexible dielectric film configured to conform to a shape of the heatsink and a metal interconnect structure formed on the flexible dielectric film and that extends through vias formed in the flexible dielectric film so as to be electrically connected to the connection pads of the LES chips.
摘要翻译： 公开了一种用于封装发光半导体（LES）的系统和方法。 提供了一种LES装置，其包括散热器和安装在散热器上并电连接到其上的LES芯片阵列，每个LES芯片包括连接焊盘和配置为响应于接收的电力从其发射光的发光区域。 LES装置还包括位于每个LES芯片上并电连接到每个LES芯片以提供LES芯片阵列的控制操作的柔性互连结构，其中柔性互连结构还包括被配置为符合散热器形状的柔性介电膜 以及金属互连结构，其形成在柔性电介质膜上并且延伸穿过形成在柔性电介质膜中的通孔，以便电连接到LES芯片的连接焊盘。
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公开(公告)号：US20130062630A1
公开(公告)日：2013-03-14
申请号：US13231547
申请日：2011-09-13
CPC分类号： H05K1/189 , H01L25/0753 , H01L27/15 , H01L33/005 , H01L33/60 , H01L33/62 , H01L33/64 , H01L33/642 , H01L33/647 , H01L2224/24 , H01L2933/0066 , H01L2933/0075 , H05K1/021 , H05K2201/10106
摘要： A system and method for packaging light emitting semiconductors (LESs) is disclosed. An LES device is provided that includes a heatsink and an array of LES chips mounted on the heatsink and electrically connected thereto, with each LES chip comprising connection pads and a light emitting area configured to emit light therefrom responsive to a received electrical power. The LES device also includes a flexible interconnect structure positioned on and electrically connected to each LES chip to provide for controlLES operation of the array of LES chips, with the flexible interconnect structure further including a flexible dielectric film configured to conform to a shape of the heatsink and a metal interconnect structure formed on the flexible dielectric film and that extends through vias formed in the flexible dielectric film so as to be electrically connected to the connection pads of the LES chips.
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公开(公告)号：US20120161325A1
公开(公告)日：2012-06-28
申请号：US13349598
申请日：2012-01-13
IPC分类号： H01L23/522
CPC分类号： H01L24/82 , H01L21/486 , H01L24/06 , H01L24/24 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/83 , H01L24/92 , H01L25/0655 , H01L25/072 , H01L2224/04105 , H01L2224/0603 , H01L2224/06181 , H01L2224/2405 , H01L2224/2413 , H01L2224/24225 , H01L2224/27416 , H01L2224/27436 , H01L2224/2919 , H01L2224/32225 , H01L2224/73217 , H01L2224/73267 , H01L2224/83191 , H01L2224/83192 , H01L2224/83194 , H01L2224/8385 , H01L2224/83862 , H01L2224/83865 , H01L2224/83874 , H01L2224/92144 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01049 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/13026 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/15787 , H01L2924/18162 , H01L2924/00
摘要： A semiconductor device package is provided. The semiconductor device package includes a laminate comprising a first metal layer disposed on a dielectric film; a plurality of vias extending through the laminate according to a predetermined pattern; one or more semiconductor devices attached to the dielectric film such that the semiconductor device contacts one or more vias; a patterned interconnect layer disposed on dielectric film, said patterned interconnect layer comprising one or more patterned regions of the first metal layer and an electrically conductive layer, wherein a portion of the patterned interconnect layer extends through one or more vias to form an electrical contact with the semiconductor device. The patterned interconnect layer comprises a top interconnect region and a via interconnect region, wherein the package interconnect region has a thickness greater than a thickness of the via interconnect region.
摘要翻译： 提供半导体器件封装。 所述半导体器件封装包括：层叠体，其包含设置在电介质膜上的第一金属层; 根据预定图案延伸穿过层压体的多个通孔; 一个或多个半导体器件连接到电介质膜，使得半导体器件接触一个或多个通孔; 设置在电介质膜上的图案化互连层，所述图案化互连层包括第一金属层的一个或多个图案化区域和导电层，其中图案化互连层的一部分延伸穿过一个或多个通孔以形成与 半导体器件。 图案化互连层包括顶部互连区域和通孔互连区域，其中封装互连区域的厚度大于通孔互连区域的厚度。
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公开(公告)号：US20120146234A1
公开(公告)日：2012-06-14
申请号：US12962761
申请日：2010-12-08
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/3171 , H01L21/56 , H01L23/3164 , H01L23/3192 , H01L24/19 , H01L24/20 , H01L29/0657 , H01L2224/24 , H01L2224/24011 , H01L2224/2402 , H01L2224/24227 , H01L2224/76155 , H01L2224/82 , H01L2224/82102 , H01L2224/82105 , H01L2224/92144 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/10155 , H01L2924/12036 , H01L2924/1204 , H01L2924/12042 , H01L2924/12043 , H01L2924/00
摘要： A semiconductor device package includes a semiconductor device having connection pads formed thereon, with the connection pads being formed on first and second surfaces of the semiconductor device with edges of the semiconductor device extending therebetween. A first passivation layer is applied on the semiconductor device and a base dielectric laminate is affixed to the first surface of the semiconductor device that has a thickness greater than that of the first passivation layer. A second passivation layer having a thickness greater than that of the first passivation layer is applied over the first passivation layer and the semiconductor device to cover the second surface and the edges of the semiconductor device, and metal interconnects are coupled to the connection pads, with the metal interconnects extending through vias formed through the first and second passivation layers and the base dielectric laminate sheet to form a connection with the connection pads.
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公开(公告)号：US09117813B2
公开(公告)日：2015-08-25
申请号：US13524369
申请日：2012-06-15
IPC分类号： H01L21/00 , H01L23/498 , H01L23/538 , H01L23/00 , H01L21/48 , H01L21/683 , H05K3/30
CPC分类号： H01L25/0655 , H01L21/4857 , H01L21/486 , H01L21/6836 , H01L23/49822 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L24/19 , H01L24/20 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/83 , H01L24/92 , H01L24/94 , H01L25/50 , H01L2221/68327 , H01L2221/6834 , H01L2221/68381 , H01L2224/04105 , H01L2224/2101 , H01L2224/221 , H01L2224/27003 , H01L2224/27312 , H01L2224/27318 , H01L2224/2732 , H01L2224/2741 , H01L2224/27416 , H01L2224/27418 , H01L2224/27422 , H01L2224/27436 , H01L2224/2781 , H01L2224/27848 , H01L2224/2919 , H01L2224/32225 , H01L2224/83101 , H01L2224/83191 , H01L2224/83192 , H01L2224/83855 , H01L2224/83856 , H01L2224/92 , H01L2224/9202 , H01L2224/92144 , H01L2224/94 , H01L2924/07802 , H01L2924/12042 , H01L2924/3511 , H05K3/305 , H01L2224/27 , H01L2224/83 , H01L2224/19 , H01L21/78 , H01L2924/00013 , H01L2924/00014 , H01L2924/0665 , H01L2924/00
摘要： A chip package includes a first die with an active surface having at least one die pad positioned thereon; a first adhesive layer having a first surface coupled to the active surface of the first die and a second surface opposite the first surface; and a first dielectric layer having a top surface. A first portion of the top surface of the first dielectric layer is coupled to the second surface of the first adhesive layer. A second portion of the top surface of the first dielectric layer, distinct from the first portion, is substantially free of adhesive.
摘要翻译： 芯片封装包括具有活性表面的第一裸片，其中至少一个芯片焊盘位于其上; 第一粘合剂层，其具有联接到第一管芯的有效表面的第一表面和与第一表面相对的第二表面; 以及具有顶表面的第一电介质层。 第一电介质层的顶表面的第一部分耦合到第一粘合剂层的第二表面。 与第一部分不同的第一介电层的顶表面的第二部分基本上没有粘合剂。
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公开(公告)号：US08114712B1
公开(公告)日：2012-02-14
申请号：US12975466
申请日：2010-12-22
CPC分类号： H01L24/82 , H01L21/486 , H01L24/06 , H01L24/24 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/83 , H01L24/92 , H01L25/0655 , H01L25/072 , H01L2224/04105 , H01L2224/0603 , H01L2224/06181 , H01L2224/2405 , H01L2224/2413 , H01L2224/24225 , H01L2224/27416 , H01L2224/27436 , H01L2224/2919 , H01L2224/32225 , H01L2224/73217 , H01L2224/73267 , H01L2224/83191 , H01L2224/83192 , H01L2224/83194 , H01L2224/8385 , H01L2224/83862 , H01L2224/83865 , H01L2224/83874 , H01L2224/92144 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01049 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/13026 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/15787 , H01L2924/18162 , H01L2924/00
摘要： A method of fabricating a semiconductor device package is provided. The method includes providing a laminate comprising a dielectric film disposed on a first metal layer, said laminate having a dielectric film outer surface and a first metal layer outer surface; forming a plurality of vias extending through the laminate according to a predetermined pattern; attaching one or more semiconductor device to the dielectric film outer surface such that the semiconductor device contacts one or more vias after attachment; disposing an electrically conductive layer on the first metal layer outer surface and on an inner surface of the plurality of vias to form an interconnect layer comprising the first metal layer and the electrically conductive layer; and patterning the interconnect according to a predetermined circuit configuration to form a patterned interconnect layer, wherein a portion of the patterned interconnect layer extends through one or more vias to form an electrical contact with the semiconductor device. A semiconductor device package is also provided.
摘要翻译： 提供一种制造半导体器件封装的方法。 该方法包括提供一种层叠体，其包含布置在第一金属层上的电介质膜，所述层压体具有电介质膜外表面和第一金属层外表面; 根据预定图案形成延伸穿过层叠体的多个通孔; 将一个或多个半导体器件附接到电介质膜外表面，使得半导体器件在附接之后接触一个或多个通孔; 在所述第一金属层外表面上和所述多个通孔的内表面上设置导电层以形成包括所述第一金属层和所述导电层的互连层; 以及根据预定电路配置图案化所述互连以形成图案化互连层，其中所述图案化互连层的一部分延伸穿过一个或多个通孔以与所述半导体器件形成电接触。 还提供了半导体器件封装。
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