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    Water-based ink for inkjet printing
    1.
    发明申请
    Water-based ink for inkjet printing 审中-公开
    水性墨水用于喷墨印刷

    公开(公告)号：US20070213428A1

    公开(公告)日：2007-09-13

    申请号：US11714855

    申请日：2007-03-07

    申请人： Atsushi Hiraishi ,  Takehiro Tsutsumi

    发明人： Atsushi Hiraishi ,  Takehiro Tsutsumi

    IPC分类号： C09D11/00 ,  B60C1/00

    CPC分类号： C09D11/322 ,  C09D11/30

    摘要： A water dispersion for inkjet printing which includes water-insoluble polymer particles. The water-insoluble polymer particles contain silica particles and a pigment other than the silica particles. A water-based ink containing the water dispersion is excellent in the storage stability and effectively reduces the bronze phenomenon of printed images.

    摘要翻译： 用于喷墨印刷的水分散体，其包括水不溶性聚合物颗粒。 水不溶性聚合物粒子含有二氧化硅粒子和二氧化硅粒子以外的颜料。 含有水分散体的水性油墨的储存稳定性优异，有效地减少了印刷图像的青铜现象。

    Apparatus having a wiring board and memory devices
    2.
    发明授权
    Apparatus having a wiring board and memory devices 有权
    具有接线板和存储器件的设备

    公开(公告)号：US08922029B2

    公开(公告)日：2014-12-30

    申请号：US13363396

    申请日：2012-02-01

    申请人： Atsushi Hiraishi ,  Toshio Sugano ,  Masahiro Yamaguchi ,  Yoji Nishio ,  Tsutomu Hara ,  Koichiro Aoki

    发明人： Atsushi Hiraishi ,  Toshio Sugano ,  Masahiro Yamaguchi ,  Yoji Nishio ,  Tsutomu Hara ,  Koichiro Aoki

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  G11C5/06 ,  G11C5/04 ,  G11C8/14 ,  H05K1/18

    CPC分类号： G11C5/063 ,  G11C5/04 ,  G11C8/14 ,  H05K1/181 ,  H05K2201/09254 ,  H05K2201/09263 ,  H05K2201/10159 ,  Y02P70/611

    摘要： An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TL0 from the data transferring element to a first branch point S1 where a branch line is branched at a shortest distance from the data transferring element is configured to become equal to or greater than a wiring length TL1 from the first branch point S1 to a second branch point S2 where a second branch line is branched. A wiring length TL3 from the second branch point S2 to a third branch point S3 where a third branch line is branched is configured to become greater than the wiring lengths TL0 and TL1.

    摘要翻译： 具有短截线结构的地址信号线连接在至少三个存储器元件和数据传输元件之间，并传送存储器元件的地址信号。 数据传送元件的地址端子的阻抗低于地址信号线的特性阻抗。 从数据传送元件到分支线从数据传送元件到最短距离分支的第一分支点S1的布线长度TL0被配置成等于或大于从第一分支点S1到布线长度TL1 第二分支点S2，其中第二支线被分支。 从第二分支点S2到分支第三分支线的第三分支点S3的布线长度TL3被配置为变得大于布线长度TL0和TL1。

    SRAM having load transistor formed above driver transistor
    6.
    发明授权
    SRAM having load transistor formed above driver transistor 失效
    具有形成在驱动晶体管上方的负载晶体管的SRAM

    公开(公告)号：US5834851A

    公开(公告)日：1998-11-10

    申请号：US460641

    申请日：1995-06-02

    申请人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

    发明人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

    IPC分类号： H01L27/11

    CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

    摘要： Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially. The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.The source line is formed of a conductive layer identical to that of the word line. The individual data lines of the complementary data line are formed of an identical conductive layer which is different from that of the word line and the source line. The identical conductive layer between the word line and source line and the complementary data line is formed with two word lines: a main word line extended in the first direction identical to that of the word line and source line and used by adopting the divided word line system: and a sub-word line used by adopting the double word line system.

    摘要翻译： 这里公开了一种半导体集成电路器件，其包括具有其存储单元的SRAM，SRAM由通过字线控制的转移MISFET和驱动MISFET构成。 驱动MISFET的栅电极和存储单元的转移MISFET的栅电极和字线分别由不同的导电层形成。 驱动MISFET和转移MISFET分别布置成在栅极长度方向上彼此交叉。 字线在驱动MISFET的栅电极的栅极长度方向上延伸，并且部分地与驱动MISFET的栅电极交叉。 存储器单元的两个转移MISFET的各自的栅极电极与彼此间隔开并沿相同方向延伸的两个相应字线连接。 由两个字线限定的区域配置有两个驱动MISFET和源极线。 源极线由与字线的导电层相同的导电层形成。 互补数据线的各个数据线由与字线和源极线不同的导电层形成。 字线和源极线与互补数据线之间的相同的导电层由两条字线形成：主字线在第一方向上延伸，与字线和源极线相同，并通过采用分割字线 系统：采用双字线系统使用的子字线。

    Signal transition detector circuit
    7.
    发明授权
    Signal transition detector circuit 失效
    信号转换检测电路

    公开(公告)号：US5680066A

    公开(公告)日：1997-10-21

    申请号：US182699

    申请日：1994-01-13

    申请人： Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yuji Yokoyama ,  Nozomu Matsuzaki ,  Tatsumi Yamauchi ,  Yutaka Kobayashi ,  Nobuyuki Gotou ,  Akira Ide ,  Masahiro Yamamura ,  Hideaki Uchida

    发明人： Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yuji Yokoyama ,  Nozomu Matsuzaki ,  Tatsumi Yamauchi ,  Yutaka Kobayashi ,  Nobuyuki Gotou ,  Akira Ide ,  Masahiro Yamamura ,  Hideaki Uchida

    IPC分类号： G11C7/10 ,  G11C8/06 ,  G11C8/10 ,  G11C8/18 ,  H03K5/1534 ,  H03K19/0175 ,  H03K5/153 ,  G01R29/02 ,  H03K3/033

    CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C8/06 ,  G11C8/10 ,  G11C8/18 ,  H03K19/017518 ,  H03K5/1534

    摘要： A semiconductor device which includes at least one of (1) an input buffer circuit formed of an input level converter and a non-inverting buffer circuit and an inverting buffer circuit each including BiCMOS circuitry which effects high-speed operation; (2) a decoder circuit formed of plural logic gates each of which is composed of the combination of MOS and bipolar circuitry; (3) a sense amplifier circuit including a multiemitter transistor; (4) a signal or address transition detector circuit which includes input circuits each receiving, for example, an address signal of a voltage amplitude and outputting a current amplitude signal in response to a change in level of the address signal, and a detector circuit connected thereto which has a cascode amplifier arranged such that it receives current amplitude signals at an input thereof and in which the cascode amplifier input is maintained at a substantially constant voltage, in which the detection circuit detects a transition of one or more of the current amplitude signals and, in response thereto, generates an ATD signal of a voltage amplitude; and (5) an output buffer circuit, in which the decoder, sense amplifier and output buffer of the device such as for a memory are controlled in accordance with signals from a clock generator, which is responsive to the ATD signal.

    摘要翻译： 一种半导体器件，其包括以下中的至少一个：（1）由输入电平转换器和非反相缓冲电路构成的输入缓冲电路和各自包括实现高速操作的BiCMOS电路的反相缓冲电路; （2）由多个逻辑门形成的解码器电路，每个逻辑门由MOS和双极电路的组合组成; （3）包括多端子晶体管的读出放大器电路; （4）信号或地址转换检测器电路，其包括各自接收例如电压幅度的地址信号并且响应于地址信号的电平的变化而输出当前振幅信号的输入电路，以及连接的检测器电路 具有共源共栅放大器，其布置成使得其在其输入处接收电流幅度信号，并且其中共源共栅放大器输入保持在基本上恒定的电压，其中检测电路检测到一个或多个当前幅度信号的转变 并且响应于此产生电压幅度的ATD信号; 以及（5）输出缓冲器电路，其中根据来自响应于ATD信号的时钟发生器的信号来控制诸如存储器的装置的解码器，读出放大器和输出缓冲器。

    Semiconductor integrated circuit having logic gates
    8.
    发明授权
    Semiconductor integrated circuit having logic gates 失效
    具有逻辑门的半导体集成电路

    公开(公告)号：US5387827A

    公开(公告)日：1995-02-07

    申请号：US643372

    申请日：1991-01-22

    申请人： Yuji Yokoyama ,  Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Nobuyuki Gotou ,  Akira Ide

    发明人： Yuji Yokoyama ,  Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Nobuyuki Gotou ,  Akira Ide

    IPC分类号： G11C7/10 ,  G11C8/10 ,  H03K19/0948 ,  H03K19/23

    CPC分类号： H03K19/0948 ,  G11C7/1051 ,  G11C7/1078 ,  G11C8/10

    摘要： A semiconductor integrated logic circuit is provided which includes a plurality of logic gates each having a first input terminal for respectively receiving first input signals, wherein each of the logic gates is coupled to a common node. In one embodiment, first and second switching elements are also coupled to the common node. The first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to the plurality of logic gates, and both operate complementary to one another in response to the second input signal. This arrangement is particularly effective for decoders in semiconductor memory circuits which use a common NMOS to receive one input for a plurality of logic decoder gates. An improved read/write arrangement is also provided for semiconductor memory circuits which includes circuitry to prevent connection of a common read line to the data lines during the writing operation. This enhances the writing speed by removing the load of the common read line during writing.

    摘要翻译： 提供了一种半导体集成逻辑电路，其包括多个逻辑门，每个逻辑门具有用于分别接收第一输入信号的第一输入端，其中每个逻辑门耦合到公共节点。 在一个实施例中，第一和第二开关元件也耦合到公共节点。 第一和第二开关元件都耦合到第二输入端子，用于接收多个逻辑门公共的第二输入信号，并且它们都响应于第二输入信号互相互补。 这种布置对于使用公共NMOS来接收多个逻辑解码器门的一个输入的半导体存储器电路中的解码器特别有效。 还提供了一种用于半导体存储器电路的改进的读/写布置，其包括在写入操作期间防止公共读取线连接到数据线的电路。 这通过在写入期间去除公共读取线的负载来增强写入速度。

    Semiconductor device
    9.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09368185B2

    公开(公告)日：2016-06-14

    申请号：US14508744

    申请日：2014-10-07

    申请人： Shunichi Saito ,  Toshio Sugano ,  Atsushi Hiraishi

    发明人： Shunichi Saito ,  Toshio Sugano ,  Atsushi Hiraishi

    IPC分类号： G11C16/26 ,  G11C11/406

    CPC分类号： G11C11/40615 ,  G11C11/40603 ,  G11C16/26

    摘要： A semiconductor device includes a plurality of memory cells, an access circuit configured to perform a data read operation, a data write operation and a data refresh operation on the memory cells, the access circuit to operate in a selected one of a first mode that is ready to perform and a second mode that is not ready to perform, and a judgment circuit configured to respond to first command information, to cause, when the access circuit is in the first mode, the access circuit to perform the data refresh operation, and to cause, when the access circuit is in the second mode, the access circuit to exit from the second mode and then to perform the refresh operation.

    摘要翻译： 半导体器件包括多个存储器单元，存取电路，被配置为对存储器单元执行数据读取操作，数据写入操作和数据刷新操作，所述存取电路以选择的第一模式操作 准备执行的第二模式和未准备好执行的第二模式;以及判断电路，被配置为响应于第一命令信息，以使得当访问电路处于第一模式时，访问电路执行数据刷新操作，以及 当访问电路处于第二模式时，访问电路从第二模式退出，然后执行刷新操作。

    Aqueous ink for inkjet recording
    10.
    发明授权
    Aqueous ink for inkjet recording 失效
    用于喷墨记录的水性油墨

    公开(公告)号：US08394871B2

    公开(公告)日：2013-03-12

    申请号：US13131221

    申请日：2009-11-20

    申请人： Atsushi Hiraishi ,  Masayuki Narita ,  Takahiro Sato ,  Kyoichi Shirota ,  Yasuhiro Doi ,  Hiroyuki Yoshida ,  Yusuke Shimizu

    发明人： Atsushi Hiraishi ,  Masayuki Narita ,  Takahiro Sato ,  Kyoichi Shirota ,  Yasuhiro Doi ,  Hiroyuki Yoshida ,  Yusuke Shimizu

    IPC分类号： C09D11/10

    CPC分类号： C09D11/322 ,  C09D11/326

    摘要： The present invention provides [1] a water dispersion for ink-jet printing containing chain-like particles each containing anionic organic pigment particles and a cationic polymer, wherein the ratio of organic pigment primary particles forming the chain-like particles to all the pigment primary particles contained in the water dispersion is 10% by number or more; [2] a water-based ink for ink-jet printing containing the water dispersion; [3] a method for producing a water dispersion for ink-jet printing as described above in [1]; and [4] a water-based ink for ink-jet printing containing a water dispersion produced through the method. The water dispersion and water-based ink for ink-jet printing of the present invention realize excellent optical density.

    摘要翻译： 本发明提供[1]一种喷墨印刷用水分散体，其含有各自含有阴离子性有机颜料粒子和阳离子性聚合物的链状粒子，其中，形成链状粒子的有机颜料一次粒子与全部颜料原料的比例 包含在水分散体中的颗粒为10个数量以上; [2]一种含有水分散体的喷墨印刷用水性油墨; [3]如上述[1]所述的喷墨打印用水分散体的制造方法， 和[4]一种用于喷墨印刷的水性油墨，其含有通过该方法制备的水分散体。 本发明的喷墨印刷用水分散体和水性油墨实现优异的光密度。