公开(公告)号：US06333551B1

公开(公告)日：2001-12-25

申请号：US09656941

申请日：2000-09-07

申请人： David V. Caletka ,  Eric A. Johnson

发明人： David V. Caletka ,  Eric A. Johnson

IPC分类号： H01L2310

CPC分类号： H01L24/83 ,  H01L23/3737 ,  H01L24/29 ,  H01L2224/2919 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/00 ,  H01L2924/3512

摘要： A method and structure for coupling a heat conductor (e.g., heat spreader, heat sink) to a semiconductor chip. In a first embodiment, a thermally conductive shape is formed on the heat conductor, a material in an uncured or partially cured state is dispensed on the chip and on peripheral portions of the chip, and the heat conductor is applied to the material to push the thermally conductive shape into the material such that the material is redistributed to contact both the thermally conductive shape and the chip. The material is then cured (e.g., by pressurization at elevated temperature). In a second embodiment, a thermally conductive shape is formed on the chip, a material (e.g., epoxy) in an uncured or partially cured state is dispensed on the thermally conductive shape and on peripheral portions of the chip, and the heat conductor is pushed into the material to make the material contact both the thermally conductive shape and the heat conductor. The material is then cured (e.g., by pressurization at elevated temperature). For both the first embodiment and the second embodiment, an average thickness of a peripheral portion of the cured material exceeds an average thickness of a central portion of the cured material.

摘要翻译： 一种用于将热导体（例如，散热器，散热器）耦合到半导体芯片的方法和结构。 在第一实施例中，在导热体上形成导热形状，将未固化或部分固化状态的材料分配在芯片上和芯片周边部分上，并将热导体施加到材料上以推动 导热形状进入材料，使得材料重新分布以接触导热形状和芯片。 然后将材料固化（例如，通过在升高的温度下加压）。 在第二实施例中，在芯片上形成导热形状，将未固化或部分固化状态的材料（例如，环氧树脂）分配在导热形状和芯片的周边部分上，并且热导体被推动 进入材料以使材料接触导热形状和导热体。 然后将材料固化（例如，通过在升高的温度下加压）。 对于第一实施例和第二实施例，固化材料的周边部分的平均厚度超过固化材料的中心部分的平均厚度。

公开(公告)号：US06293455B1

公开(公告)日：2001-09-25

申请号：US09649318

申请日：2000-08-28

申请人： David V. Caletka ,  Kevin Knadle ,  Charles G. Woychik

发明人： David V. Caletka ,  Kevin Knadle ,  Charles G. Woychik

IPC分类号： B23K3112

CPC分类号： B23K3/08 ,  H05K1/0201 ,  H05K3/3494 ,  H05K2201/10151 ,  H05K2203/081 ,  H05K2203/1121

摘要： A method and an arrangement for measuring the cooling rate and thermal gradient between the top and bottom surfaces of a printed circuit board. Moreover, it is intended to facilitate control over the temperature gradient which is encountered between the top and bottom of the PCB so as to prevent warpage thereof during the formation of solder joints in a reflow solder oven.

摘要翻译： 一种用于测量印刷电路板的顶表面和底表面之间的冷却速率和热梯度的方法和装置。 此外，旨在便于控制PCB顶部和底部之间遇到的温度梯度，以防止在回流焊料炉中形成焊点期间的翘曲。

公开(公告)号：US06274474B1

公开(公告)日：2001-08-14

申请号：US09426578

申请日：1999-10-25

申请人： David V. Caletka ,  Eric A. Johnson

发明人： David V. Caletka ,  Eric A. Johnson

IPC分类号： H01L2144

CPC分类号： H01L24/81 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K1/111 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/094 ,  H05K2201/0989 ,  H05K2201/099 ,  Y02P70/613 ,  H01L2924/00

摘要： A method of forming BGA interconnections having improved fatigue life is disclosed. In particular, a combination of mask-defined and pad-defined solder joints are selectively positioned within the BGA package. The mask-defined solder joints possess a high equilibrium height, which forces the pad-defined solder joints to elongate, thereby making the pad-defined solder joints more compliant. Further, the pad-defined solder joints posses a slightly longer fatigue life because the stress concentrations found in the mask-defined solder joints are not present in the pad-defined solder joints. Therefore, the fatigue life of BGA packages is increased by implementing a majority of mask-defined solder joints to maintain a high equilibrium height, and selectively placing pad-defined solder joints in high stress areas of the BGA package.

摘要翻译： 公开了一种形成具有改善的疲劳寿命的BGA互连的方法。 特别地，掩模限定和限定焊点的组合被选择性地定位在BGA封装内。 掩模定义的焊点具有高的平衡高度，这迫使焊盘限定的焊点伸长，从而使焊盘限定的焊点更顺应。 此外，焊盘限定的焊接接头具有稍长的疲劳寿命，因为在焊盘限定的焊点中不存在在掩模限定的焊点中发现的应力集中。 因此，通过实施大多数掩模定义的焊点以保持高平衡高度，并且将焊盘限定的焊点选择性地放置在BGA封装的高应力区域中，从而增加了BGA封装的疲劳寿命。

公开(公告)号：US06268567B1

公开(公告)日：2001-07-31

申请号：US09491066

申请日：2000-01-25

申请人： William L. Brodsky ,  David V. Caletka ,  William infantolino

发明人： William L. Brodsky ,  David V. Caletka ,  William infantolino

IPC分类号： H01B708

CPC分类号： H01B7/08 ,  H01B7/0072

摘要： A ribbon cable includes electrical conductors surrounded by an insulator and vent tubes positioned adjacent and parallel to the conductors and insulator. The vent tubes allow airflow between an internal area of the enclosure and an external atmosphere and prevent access to the internal area of the enclosure.

公开(公告)号：US07510912B2

公开(公告)日：2009-03-31

申请号：US11822573

申请日：2007-07-09

申请人： David V. Caletka ,  Varaprasad V. Calmidi ,  Sanjeev Sathe

发明人： David V. Caletka ,  Varaprasad V. Calmidi ,  Sanjeev Sathe

IPC分类号： H01L21/00

CPC分类号： H01L23/3128 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/49838 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/48647 ,  H01L2224/48747 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/8385 ,  H01L2224/85447 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K1/0203 ,  H05K3/3436 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/3512

摘要： A method of making a wirebond electronic package which includes a semiconductor chip bonded to the upper surface of an organic laminate substrate, including to a thermal material located on the substrate and comprised of a plurality of thermally conductive concentric lines. These lines form paths of heat escape for the chip during operation thereof and may operate in combination with other elements to extend the heat paths. Concentric lines also assure sufficient bonding area on the substrate so as to prevent delamination of the chip from the substrate as may occur during high temperatures associated with subsequent processing such as solder ball re-flow.

摘要翻译： 一种制造引线键合电子封装的方法，其包括结合到有机层叠基板的上表面的半导体芯片，该半导体芯片包括位于基板上并由多个导热同心线组成的热材料。 这些线在其操作期间形成芯片的热逸出路径，并且可以与其它元件结合操作以延伸热路径。 同心线还确保了衬底上足够的结合面积，以防止芯片与衬底分层，这可能与随后的处理（例如焊球重新流动）相关的高温期间可能发生。

公开(公告)号：US07499614B2

公开(公告)日：2009-03-03

申请号：US10692921

申请日：2003-10-24

申请人： Eric A. Johnson ,  David V. Caletka

发明人： Eric A. Johnson ,  David V. Caletka

IPC分类号： G02B6/26

CPC分类号： G02B6/1221 ,  G02B6/12004 ,  G02B6/42 ,  G02B6/4232 ,  G02B2006/12104 ,  G02B2006/12176

摘要： A method of producing opto-electronic cards and printed circuit boards which are adapted to provide for passive alignment of VCSELs to waveguides. Also provided are opto-electronic cards and printed circuit boards which incorporate structure providing for the passive alignment of VCSELs to waveguides.

摘要翻译： 一种制造光电卡和印刷电路板的方法，其适于提供VCSEL与波导的无源对准。 还提供了光电卡和印刷电路板，其结合提供VCSEL到波导的被动对准的结构。

公开(公告)号：US06410988B1

公开(公告)日：2002-06-25

申请号：US09570895

申请日：2000-05-15

申请人： David V. Caletka ,  Jean Dery ,  Eric Duchesne ,  Michael A. Gaynes ,  Eric A. Johnson ,  Luis J. Matienzo ,  James R. Wilcox

发明人： David V. Caletka ,  Jean Dery ,  Eric Duchesne ,  Michael A. Gaynes ,  Eric A. Johnson ,  Luis J. Matienzo ,  James R. Wilcox

IPC分类号： H01L2348

CPC分类号： H01L23/4334 ,  H01L23/3128 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/3512

摘要： A method of making a flip chip package that maintains flatness over a wide temperature range and provides good heat dissipation is described. A laminate substrate is electrically connected to electrical contacts disposed on a chip and underfill material is applied between the soldered connections. A body, for example an uncured dielectric material, is applied to the chip, the laminate substrate, a thermally conductive member or combinations thereof, and thermally conductive member is disposed adjacent to the surface of the chip that is opposite the surface connected to the laminate substrate. The body is extruded between the chip and the thermally conductive member. The thickness of the thermally conductive member is determined by balancing the stiffness and the CTE of both the thermally conductive member and the laminate substrate, and the length and width of the thermally conductive member may vary but are at least the size of the corresponding length and width of the chip.

摘要翻译： 描述了制造在宽温度范围内保持平坦度并提供良好散热的倒装芯片封装的方法。 层压基板电连接到设置在芯片上的电触头，底部填充材料被施加在焊接连接之间。 例如未固化介电材料的主体被施加到芯片，层压基板，导热构件或其组合，并且导热构件设置在与连接到层压板的表面相对的芯片的表面附近 基质。 主体在芯片和导热构件之间挤出。 导热构件的厚度通过平衡导热构件和层压衬底的刚度和CTE来确定，并且导热构件的长度和宽度可以变化，但是至少为相应长度的尺寸，并且 芯片的宽度。

公开(公告)号：US6104093A

公开(公告)日：2000-08-15

申请号：US80117

申请日：1998-05-15

申请人： David V. Caletka ,  Jean Dery ,  Eric Duchesne ,  Michael A. Gaynes ,  Eric A. Johnson ,  Luis J. Matienzo ,  James R. Wilcox

发明人： David V. Caletka ,  Jean Dery ,  Eric Duchesne ,  Michael A. Gaynes ,  Eric A. Johnson ,  Luis J. Matienzo ,  James R. Wilcox

IPC分类号： H01L23/31 ,  H01L23/433 ,  H01L23/48

CPC分类号： H01L23/4334 ,  H01L23/3128 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/10253 ,  H01L2924/15311

摘要： A method of making a flip chip package that maintains flatness over a wide temperature range and provides good heat dissipation is described. A laminate substrate is electrically connected to electrical contacts disposed on a chip and underfill material is applied between the soldered connections. A body, for example an uncured dielectric material, is applied to the chip, the laminate substrate, a thermally conductive member or combinations thereof, and thermally conductive member is disposed adjacent to the surface of the chip that is opposite the surface connected to the laminate substrate. The body is extruded between the chip and the thermally conductive member. The thickness of the thermally conductive member is determined by balancing the stiffness and the CTE of both the thermally conductive member and the laminate substrate, and the length and width of the thermally conductive member may vary but are at least the size of the corresponding length and width of the chip.

公开(公告)号：US5873740A

公开(公告)日：1999-02-23

申请号：US4681

申请日：1998-01-07

申请人： David J. Alcoe ,  William L. Brodsky ,  David V. Caletka

发明人： David J. Alcoe ,  William L. Brodsky ,  David V. Caletka

IPC分类号： H01R12/04 ,  H01R13/24 ,  H01R43/24 ,  H01R9/09

CPC分类号： H01R13/2414 ,  H01R43/24

摘要： An electrical connector assembly which utilizes a double layered elastomeric for a pressure exertion member wherein the two, individual layers are of different hardness. The first layer is of a relatively low durometer elastomeric material while the second layer is of higher durometer elastomeric material and includes several projections, e.g., for engaging a circuitized substrate such as a flexible circuit. Both layers preferably have the same spring rate, while the projections of the second layer may possess a variety of different configurations, e.g., cylindrical or boxlike. The individual projections may each include extension portions which in turn are positioned within corresponding openings within the substantially solid first layer.

摘要翻译： 一种电连接器组件，其使用双层弹性体用于压力消耗构件，其中两个单独的层具有不同的硬度。 第一层具有相对较低的硬度弹性体材料，而第二层具有较高硬度的弹性体材料，并且包括多个突起，例如用于接合诸如柔性电路的电路化基底。 两层优选地具有相同的弹簧速率，而第二层的突起可以具有各种不同的构造，例如圆柱形或盒状。 各个突起可以各自包括延伸部分，该延伸部分又位于基本上固体的第一层内的对应的开口内。

公开(公告)号：US07875811B2

公开(公告)日：2011-01-25

申请号：US12010335

申请日：2008-01-24

申请人： David V. Caletka ,  Frank D. Egitto

发明人： David V. Caletka ,  Frank D. Egitto

IPC分类号： H01R12/04 ,  H05K1/11

CPC分类号： H05K1/0219 ,  H01R12/523 ,  H01R13/2414 ,  H05K1/113 ,  H05K3/4046 ,  H05K3/429 ,  H05K3/4614 ,  H05K2201/0959 ,  H05K2201/09809 ,  H05K2201/10303 ,  H05K2201/10378 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A high speed interposer which includes a substrate having alternatingly oriented dielectric and conductive layers which form a substrate, openings which extend from one opposing surface of the substrate to a second opposing surface, conductive members positioned within the openings and also extending from surface to surface (and beyond, in some embodiments), and a plurality of shielding members positioned substantially around the conductive members to provide shielding therefore during the passage of high frequency signals through the conductive members.

摘要翻译： 高速插入器，其包括具有交替取向的介电层和导电层的基板，其形成基板，从基板的一个相对表面延伸到第二相对表面的开口，定位在开口内并且还从表面延伸到表面的导电构件 并且在一些实施例中超越）以及基本上围绕导电构件定位的多个屏蔽构件，从而在高频信号通过导电构件期间提供屏蔽。