公开(公告)号：US07024764B2

公开(公告)日：2006-04-11

申请号：US10040745

申请日：2002-01-07

申请人： John S. Kresge ,  Robert D. Sebesta ,  David B. Stone ,  James R. Wilcox

发明人： John S. Kresge ,  Robert D. Sebesta ,  David B. Stone ,  James R. Wilcox

IPC分类号： H05K3/34

CPC分类号： H01L23/49822 ,  H01L23/3735 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/114 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4641 ,  H05K2201/0191 ,  H05K2201/068 ,  H05K2201/09536 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/0401

摘要： A method of making an electronic package. The method includes forming a semiconductor chip and an multi-layered interconnect structure. The semiconductor chip includes a plurality of contact members on one of its surfaces that are connected to the multi-layered interconnect structure by a plurality of solder connections. The formed multi-layered interconnect structure is adapted for electrically interconnecting the semiconductor chip to a circuitized substrate (eg., circuit board) with another plurality of solder connections and includes a thermally conductive layer being comprised of a material having a selected thickness and coefficient of thermal expansion to substantially prevent failure of the solder connections between said first plurality of electrically conductive members and the semiconductor chip. The method forms the electronic package to further include a dielectric material having an effective modulus to assure sufficient compliancy of the multi-layered interconnect structure during operation.

摘要翻译： 制作电子包装的方法。 该方法包括形成半导体芯片和多层互连结构。 半导体芯片包括通过多个焊接连接而连接到多层互连结构的其一个表面上的多个接触构件。 形成的多层互连结构适于将半导体芯片与另外多个焊接连接的电路化基板（例如，电路板）电互连，并且包括导热层，其由具有选定厚度和系数的材料组成 热膨胀以基本上防止所述第一多个导电构件和半导体芯片之间的焊料连接的故障。 该方法形成电子封装以进一步包括具有有效模数的电介质材料，以确保在操作期间多层互连结构的充分符合性。

公开(公告)号：US06618940B2

公开(公告)日：2003-09-16

申请号：US09909211

申请日：2001-07-19

申请人： Kenneth J. Lubert ,  Curtis L. Miller ,  Thomas R. Miller ,  Robert D. Sebesta ,  James W. Wilson ,  Michael Wozniak

发明人： Kenneth J. Lubert ,  Curtis L. Miller ,  Thomas R. Miller ,  Robert D. Sebesta ,  James W. Wilson ,  Michael Wozniak

IPC分类号： H05K310

CPC分类号： H05K3/0094 ,  H05K3/061 ,  H05K3/064 ,  H05K3/427 ,  H05K2201/0166 ,  H05K2201/0209 ,  H05K2201/0959 ,  H05K2203/025 ,  H05K2203/0353 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49171

摘要： A high density printed wiring board is prepared by applying an essentially solid material into plated through holes such that the metallized layers within the through hole are unaffected by chemical metal etchants. In this manner, lateral surface metallized layers can exclusively be reduced in thickness by use of said chemical agents. These thinned lateral surface metallized layers are ultimately converted into fine pitch, 25 to 40 microns, circuitry, thereby providing high density boards. Since the through hole wall metallization is unaffected by the etching process, excellent electrical connection between the fine line circuitry is obtained. Various printed wiring board embodiments are also presented.

摘要翻译： 通过将基本上固体的材料施加到电镀的通孔中来制备高密度印刷线路板，使得通孔内的金属化层不受化学金属蚀刻剂的影响。 以这种方式，通过使用所述化学试剂，侧表面金属化层可以专门地减小厚度。 这些变薄的侧表面金属化层最终被转换为25至40微米的细间距，电路，从而提供高密度板。 由于通孔壁金属化不受蚀刻工艺的影响，所以可以获得细线电路之间的良好的电连接。 还提出了各种印刷线路板实施例。

公开(公告)号：US06291779B1

公开(公告)日：2001-09-18

申请号：US09345573

申请日：1999-06-30

申请人： Kenneth J. Lubert ,  Curtis L. Miller ,  Thomas R. Miller ,  Robert D. Sebesta ,  James W. Wilson ,  Michael Wozniak

发明人： Kenneth J. Lubert ,  Curtis L. Miller ,  Thomas R. Miller ,  Robert D. Sebesta ,  James W. Wilson ,  Michael Wozniak

IPC分类号： H05K111

CPC分类号： H05K3/0094 ,  H05K3/061 ,  H05K3/064 ,  H05K3/427 ,  H05K2201/0166 ,  H05K2201/0209 ,  H05K2201/0959 ,  H05K2203/025 ,  H05K2203/0353 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49171

摘要： A high density printed wiring board is prepared by applying an essentially solid material into plated through holes such that the metallized layers within the through hole are unaffected by chemical metal etchants. In this manner, lateral surface metallized layers can exclusively be reduced in thickness by use of said chemical agents. These thinned lateral surface metallized layers are ultimately converted into fine pitch, 25 to 40 microns, circuitry, thereby providing high density boards. Since the through hole wall metallization is unaffected by the etching process, excellent electrical connection between the fine line circuitry is obtained. Various printed wiring board embodiments are also presented.

摘要翻译： 通过将基本上固体的材料施加到电镀的通孔中来制备高密度印刷线路板，使得通孔内的金属化层不受化学金属蚀刻剂的影响。 以这种方式，通过使用所述化学试剂，侧表面金属化层可以专门地减小厚度。 这些变薄的侧表面金属化层最终被转换为25至40微米的细间距，电路，从而提供高密度板。 由于通孔壁金属化不受蚀刻工艺的影响，所以可以获得细线电路之间的良好的电连接。 还提出了各种印刷线路板实施例。

公开(公告)号：US6014809A

公开(公告)日：2000-01-18

申请号：US33618

申请日：1998-03-03

申请人： Robert D. Sebesta

发明人： Robert D. Sebesta

IPC分类号： H05K3/00 ,  H05K3/10 ,  H05K3/38 ,  H05K3/40 ,  H05K3/02

CPC分类号： H05K3/403 ,  H05K3/108 ,  H05K2201/09154 ,  H05K2203/0769 ,  H05K2203/095 ,  H05K3/0032 ,  H05K3/388 ,  H05K3/4076 ,  Y10T29/49082 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/5102

摘要： The present invention provides a method of performing high density over the edge circuitization on circuit cards. In particular, the invention allows for circuits having width and spacing requirements of one millimeter or less to be placed over the edge of a substrate. The method includes the steps of: (1) angling the substrate such that the first surface, second surface and edge separating the two surfaces form an exposed region; (2) metallically sputter seeding the exposed region from a seeding source such that a metallic sputter seed layer is formed; (3) covering the exposed region with a dielectric material; (4) ablating portions of the dielectric material; (5) applying a conductive layer, for example, with copper plating, on the circuit path to form a circuit; (6) removing the remaining unablated dielectric material, thereby exposing portions of the metallic sputter seed layer that are adjacent to the circuit; and (7) removing the exposed portions of the metallic sputter seed layer that are not part of the circuit.

摘要翻译： 本发明提供了一种在电路卡上的边缘电路上执行高密度的方法。 特别地，本发明允许具有一毫米或更小的宽度和间距要求的电路放置在衬底的边缘上。 该方法包括以下步骤：（1）使衬底倾斜，使得分离两个表面的第一表面，第二表面和边缘形成暴露区域; （2）从接种源金属溅射接触曝光区域，从而形成金属溅射种子层; （3）用介电材料覆盖所述暴露区域; （4）烧蚀介电材料的部分; （5）在电路上施加例如镀铜的导电层以形成电路; （6）去除剩余的未铺放的电介质材料，从而暴露与电路相邻的金属溅射种子层的部分; 和（7）去除金属溅射种子层的不是电路的一部分的暴露部分。

公开(公告)号：US5505320A

公开(公告)日：1996-04-09

申请号：US343162

申请日：1994-11-22

申请人： Francis C. Burns ,  Robert L. Lewis ,  Steven W. Opie ,  Robert D. Sebesta

发明人： Francis C. Burns ,  Robert L. Lewis ,  Steven W. Opie ,  Robert D. Sebesta

IPC分类号： C23F1/02 ,  H01L21/48 ,  H05K3/00 ,  H05K3/06 ,  H05K3/38 ,  H01B13/00 ,  B44C1/22 ,  C23F1/00

CPC分类号： H01L21/4846 ,  C23F1/02 ,  H05K3/061 ,  H05K3/0032 ,  H05K3/062 ,  H05K3/388

摘要： A pattern is provided on a substrate by providing the substrate with at least two layers of material thereon and providing a layer of dry imaging polymer compositions thereon. The layer of the dry imaging polymer composition is laser ablated to provide the desired personality pattern. The top exposed portion of at least the top layer is removed and the desired select pattern is laser ablated. The exposed portions of said first layer is removed and the pattern is completed through the other layers of material to thereby expose the substrate surface, without the substrate surface being subjected to laser ablating to thereby provide the desired pattern on the substrate.

摘要翻译： 通过在衬底上提供至少两层材料，并在其上提供一层干成像聚合物组合物，在衬底上提供图案。 将干成像聚合物组合物的层激光烧蚀以提供期望的个性图案。 至少顶层的顶部暴露部分被去除并且期望的选择图案被激光烧蚀。 去除所述第一层的暴露部分，并且通过其它材料层完成图案，从而暴露衬底表面，而不对衬底表面进行激光烧蚀，从而在衬底上提供期望的图案。

公开(公告)号：US06829823B2

公开(公告)日：2004-12-14

申请号：US10067551

申请日：2002-02-05

申请人： Francis J. Downes, Jr. ,  Donald S. Farquhar ,  Elizabeth Foster ,  Robert M. Japp ,  Gerald W. Jones ,  John S. Kresge ,  Robert D. Sebesta ,  David B. Stone ,  James R. Wilcox

发明人： Francis J. Downes, Jr. ,  Donald S. Farquhar ,  Elizabeth Foster ,  Robert M. Japp ,  Gerald W. Jones ,  John S. Kresge ,  Robert D. Sebesta ,  David B. Stone ,  James R. Wilcox

IPC分类号： H01K310

CPC分类号： H05K3/4641 ,  H01L21/4853 ,  H01L23/3735 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/114 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4632 ,  H05K3/4688 ,  H05K2201/0141 ,  H05K2201/0191 ,  H05K2201/068 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/10378 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/0401

摘要： A method of making a multi-layered interconnect structure. First and second electrically conductive members are formed on the first and second dielectric layers, respectively. The dielectric layer are formed on opposing surfaces of a thermally conductive layer. A first and second electrically conductive layer is formed within the first dielectric layer. The second electrically conductive layer includes shielded signal conductors and is positioned between the first electrically conductive layer and the thermally conductive layer. A plated through hole (PTH) formed through the interconnect structure is electrically connected to one of the first and second electrically conductive members and to one of the shielded signal conductors. A third dielectric layer, formed on the first dielectric layer and on portions of the first electrically conductive members, substantially overlies the PTH and includes a high density interconnect layer for providing an electrical path from an electronic device to the shielded signal conductors.

摘要翻译： 一种制造多层互连结构的方法。 第一和第二导电构件分别形成在第一和第二电介质层上。 电介质层形成在导热层的相对表面上。 第一和第二导电层形成在第一介电层内。 第二导电层包括屏蔽信号导体并且位于第一导电层和导热层之间。 通过互连结构形成的电镀通孔（PTH）电连接到第一和第二导电构件中的一个和屏蔽信号导体之一。 形成在第一介电层上和第一导电构件的部分上的第三电介质层基本上覆盖在PTH上，并且包括用于提供从电子器件到屏蔽信号导体的电气路径的高密度互连层。

公开(公告)号：US06351393B1

公开(公告)日：2002-02-26

申请号：US09346356

申请日：1999-07-02

申请人： John S. Kresge ,  Robert D. Sebesta ,  David B. Stone ,  James R. Wilcox

发明人： John S. Kresge ,  Robert D. Sebesta ,  David B. Stone ,  James R. Wilcox

IPC分类号： H05K114

CPC分类号： H01L23/49822 ,  H01L23/3735 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/114 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4641 ,  H05K2201/0191 ,  H05K2201/068 ,  H05K2201/09536 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/0401

摘要： An electronic package and method of making the electronic package is provided. The package includes a semiconductor chip and an multi-layered interconnect structure. The semiconductor chip includes a plurality of contact members on one of its surfaces that are connected to the multi-layered interconnect structure by a plurality of solder connections. The multi-layered interconnect structure is adapted for electrically interconnecting the semiconductor chip to a circuitized substrate (eg., circuit board) with another plurality of solder connections and includes a thermally conductive layer being comprised of a material having a selected thickness and coefficient of thermal expansion to substantially prevent failure of the solder connections between said first plurality of electrically conductive members and the semiconductor chip. The electronic package further includes a dielectric material having an effective modulus to assure sufficient compliancy of the multi-layered interconnect structure during operation.

摘要翻译： 提供电子封装和制造电子封装的方法。 封装包括半导体芯片和多层互连结构。 半导体芯片包括通过多个焊接连接而连接到多层互连结构的其一个表面上的多个接触构件。 多层互连结构适于将半导体芯片与另外多个焊料连接的电路化基板（例如，电路板）电互连，并且包括由具有选定厚度和热系数的材料组成的导热层 从而基本上防止所述第一多个导电构件和半导体芯片之间的焊料连接的故障。 电子封装还包括具有有效模数的电介质材料，以确保在操作期间多层互连结构的充分符合性。

公开(公告)号：US5612573A

公开(公告)日：1997-03-18

申请号：US584757

申请日：1996-01-11

申请人： Robert L. Lewis ,  Robert D. Sebesta ,  Daniel M. Waits

发明人： Robert L. Lewis ,  Robert D. Sebesta ,  Daniel M. Waits

IPC分类号： H05K1/18 ,  H01L21/48 ,  H01L21/60 ,  H01L23/12 ,  H01L23/498 ,  H01L23/538 ,  H05K1/11 ,  H05K3/34 ,  H05K3/40 ,  H05K3/46 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/4846 ,  H01L23/49816 ,  H01L23/5385 ,  H05K1/112 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/1403 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K2201/09472 ,  H05K2201/10734 ,  H05K3/3431 ,  H05K3/3436 ,  H05K3/4007 ,  H05K3/4644

摘要： A circuitized substrate for use in an electronic package wherein the substrate, e.g., ceramic, includes more than one conductive layer, e.g. , copper, thereon separated by a suitable dielectric material, e.g. , polyimide. Each layer includes its own conductive location(s) which are designed for being directly electrically connected, e.g., using solder, to respective contact sites on a semiconductor chip positioned on the substrate to form part of the final package. A method for making such a package is also provided. Significantly, the resulting package does not include interconnections between the conductive layers at the desired contact locations, these locations, as mentioned, instead being directly connected to the chip.

摘要翻译： 一种用于电子封装的电路化衬底，其中衬底例如陶瓷包括多于一个的导电层，例如陶瓷。 ，铜，其上由合适的电介质材料分隔，例如。 ，聚酰亚胺。 每个层包括其自身的导电位置，其被设计用于直接电连接（例如使用焊料）到位于衬底上的半导体芯片上的相应接触位置，以形成最终封装的一部分。 还提供了制造这种包装的方法。 显着地，所得到的封装不包括在所需接触位置处的导电层之间的互连，如上所述，这些位置而不是直接连接到芯片。

公开(公告)号：US06538213B1

公开(公告)日：2003-03-25

申请号：US09506951

申请日：2000-02-18

申请人： Timothy F. Carden ,  Todd W. Davies ,  Ross W. Keesler ,  Robert D. Sebesta ,  David B. Stone ,  Cheryl L. Tytran-Palomaki

发明人： Timothy F. Carden ,  Todd W. Davies ,  Ross W. Keesler ,  Robert D. Sebesta ,  David B. Stone ,  Cheryl L. Tytran-Palomaki

IPC分类号： H01R1204

CPC分类号： H05K1/114 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01R4/024 ,  H05K3/429 ,  H05K2201/09227 ,  H05K2201/10734

摘要： An organic integrated circuit chip carrier for high density integrated circuit chip attach, wherein the contact pads or microvias which provide electrical interconnections to external circuitry are located in a first array pattern, while the plated through holes or through-vias are located in a second array pattern. This allows utilization of wiring channels within the chip carrier in which signal wiring traces can be routed.

摘要翻译： 一种用于高密度集成电路芯片连接的有机集成电路芯片载体，其中提供与外部电路的电互连的接触焊盘或微孔位于第一阵列图案中，而电镀通孔或通孔位于第二阵列 模式。 这允许利用芯片载体内的布线通道，其中可以布线信号布线。

公开(公告)号：US06373717B1

公开(公告)日：2002-04-16

申请号：US09540172

申请日：2000-03-31

申请人： Francis J. Downes, Jr. ,  Donald S. Farquhar ,  Elizabeth Foster ,  Robert M. Japp ,  Gerald W. Jones ,  John S. Kresge ,  Robert D. Sebesta ,  David B. Stone ,  James R. Wilcox

发明人： Francis J. Downes, Jr. ,  Donald S. Farquhar ,  Elizabeth Foster ,  Robert M. Japp ,  Gerald W. Jones ,  John S. Kresge ,  Robert D. Sebesta ,  David B. Stone ,  James R. Wilcox

IPC分类号： H05K118

CPC分类号： H05K3/4641 ,  H01L21/4853 ,  H01L23/3735 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/114 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4632 ,  H05K3/4688 ,  H05K2201/0141 ,  H05K2201/0191 ,  H05K2201/068 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/10378 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/0401

摘要： An electronic package, and method of making the electronic package, is provided. The package includes a semiconductor chip and an multi-layered interconnect structure having a high density interconnect layer such as an allylated surface layer. The semiconductor chip includes a plurality of contact members on one of its surfaces that are connected to the multi-layered interconnect structure by a plurality of solder connections. The multi-layered interconnect structure is adapted for electrically interconnecting the semiconductor chip to a circuitized substrate (eg., circuit board) with another plurality of solder connections and includes a thermally conductive layer being comprised of a material having a selected thickness and coefficient of thermal expansion to substantially prevent failure of the solder connections between said first plurality of electrically conductive members and the semiconductor chip. The electronic package further includes a dielectric material having an effective modulus to assure sufficient compliancy of the multi-layered interconnect structure during operation. The allylated surface layer has the property of being able to withstand thermal stresses that arise during thermal cycling operation of the electronic package.