公开(公告)号：US07119565B2

公开(公告)日：2006-10-10

申请号：US10728304

申请日：2003-12-03

申请人： Chien-Te Chen ,  Chien-Ping Huang

发明人： Chien-Te Chen ,  Chien-Ping Huang

IPC分类号： G01R31/02

CPC分类号： H05K1/0268 ,  H05K3/222 ,  H05K3/3452 ,  H05K7/1053 ,  H05K2201/0989 ,  H05K2201/10636 ,  Y02P70/611

摘要： A chip carrier for testing electrical performance of a passive component includes: a core layer having a plurality of conductive traces on a surface thereof; at least one first trace connected with the passive component and having a first predetermined position and two ends, wherein the two ends are respectively electrically connected to a first bond finger on the surface of the chip carrier and to a first ball pad on an opposite surface of the chip carrier; at least one second trace not connected with the passive component and having two ends and a second predetermined position located on the same surface as the first predetermined position, one end of the second trace being electrically connected to a second ball pad located on the same surface as the first ball pad; and a solder mask layer applied over the conductive traces, with the first and second predetermined positions exposed.

摘要翻译： 用于测试无源部件的电性能的芯片载体包括：在其表面上具有多个导电迹线的芯层; 至少一个第一迹线与无源部件连接并且具有第一预定位置和两端，其中两端分别电连接到芯片载体表面上的第一接合指状物和相对表面上的第一球垫 的芯片载体; 至少一个第二迹线不与无源部件连接并且具有位于与第一预定位置相同的表面上的两端和第二预定位置，第二迹线的一端电连接到位于同一表面上的第二球垫 作为第一个球垫; 以及施加在导电迹线上的焊接掩模层，其中暴露第一和第二预定位置。

公开(公告)号：US06700204B2

公开(公告)日：2004-03-02

申请号：US10038732

申请日：2002-01-02

申请人： Chien-Ping Huang ,  Chien-Te Chen

发明人： Chien-Ping Huang ,  Chien-Te Chen

IPC分类号： H01R2348

CPC分类号： H05K3/3442 ,  H05K1/111 ,  H05K3/28 ,  H05K2201/09381 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/10636 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T428/24917

摘要： A substrate for accommodating a passive component is proposed, including a core layer defined with a chip attach area and a trace forming area surrounding the chip attach area, with a solder mask layer being applied on the trace forming area. At least a pair of solder pads are formed on the trace forming area, and partly exposed to outside of the solder mask layer. The solder pads are each formed at a central position with an recess, allowing the core layer to be partly exposed through the recesses of the solder pads. For bonding a passive component to the solder pads, solder paste soldered on the solder pads forms a recessed top surface due to surface tension of the solder paste, and generates a downward and convergent dragging force for properly positioning the passive component on the solder pads without producing shifting or tombstone effect.

摘要翻译： 提出了一种用于容纳无源部件的基板，包括由芯片附着区域限定的芯层和围绕芯片附着区域的迹线形成区域，在迹线形成区域上施加有阻焊层。 在迹线形成区域上形成至少一对焊盘，并且部分地暴露于焊料掩模层的外部。 焊盘各自形成在具有凹部的中心位置，允许芯层通过焊盘的凹部部分露出。 为了将无源部件焊接到焊盘，由于焊膏的表面张力焊接在焊盘上的焊膏形成凹陷的顶部表面，并且产生向下且会聚的拖曳力，以将无源部件适当地定位在焊盘上，而无需 产生转移或墓碑效应。

公开(公告)号：US20050253253A1

公开(公告)日：2005-11-17

申请号：US10974376

申请日：2004-10-26

申请人： Wen-Jung Chiang ,  Chien-Te Chen ,  Yu-Po Wang

发明人： Wen-Jung Chiang ,  Chien-Te Chen ,  Yu-Po Wang

IPC分类号： H01L23/10 ,  H01L23/367 ,  H01L23/498

CPC分类号： H01L23/49838 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A high electrical performance semiconductor package is proposed. A carrier is provided having a first surface, an opposite second surface, and conductive vias for electrically connecting the first surface to the second surface. A chip is attached to the first surface of the carrier. A plurality of via lands are disposed peripherally on the first surface of the carrier and electrically connected to the vias. A plurality of conductive regions are disposed on the second surface of the carrier and electrically connected to the vias. A plurality of fingers are disposed around the chip and electrically connected to the via lands by conductive traces formed on the first surface of the carrier. A plurality of bonding wires electrically connect the chip to the fingers. Lengths of the wires for transmitting differential pair signals are substantially equal, and lengths of the traces for transmitting the differential pair signals are substantially equal.

摘要翻译： 提出了一种高性能半导体封装。 提供具有第一表面，相对的第二表面和用于将第一表面电连接到第二表面的导电通孔的载体。 芯片附接到载体的第一表面。 多个通孔焊盘周边设置在载体的第一表面上并电连接到通孔。 多个导电区域设置在载体的第二表面上并电连接到通孔。 多个指状物设置在芯片周围，并通过形成在载体的第一表面上的导电迹线电连接到通孔焊盘。 多个接合线将芯片电连接到手指。 用于传输差分对信号的导线的长度基本相等，用于发送差分对信号的迹线的长度基本相等。

公开(公告)号：US20060049516A1

公开(公告)日：2006-03-09

申请号：US11145318

申请日：2005-06-03

申请人： Yu-Po Wang ,  Chiang-Cheng Chang ,  Chien-Te Chen

发明人： Yu-Po Wang ,  Chiang-Cheng Chang ,  Chien-Te Chen

IPC分类号： H01L23/48

CPC分类号： H05K3/243 ,  H01L21/563 ,  H01L23/49811 ,  H01L2924/0002 ,  H05K1/111 ,  H05K3/064 ,  H05K3/3452 ,  H05K2201/09845 ,  H05K2203/0542 ,  Y02P70/611 ,  H01L2924/00

摘要： A nickel/gold (Ni/Au) pad structure of a semiconductor package and a fabrication method thereof are provided. The fabrication method includes preparing a core layer; forming a conductive trace layer on the core layer; patterning the conductive trace layer to form at least one pad of the conductive trace layer; applying a conductive layer; forming a photoresist layer to define a predetermined plating region on the pad, wherein the predetermined plating region is smaller in area than the pad; forming a Ni/Au layer on the predetermined plating region; removing the photoresist layer and etching away the conductive layer; and applying a solder mask layer and forming at least one opening in the solder mask layer to expose the pad, wherein the opening is larger in area than the Ni/Au layer. The Ni/Au pad structure fabricated by the above method can prevent a solder extrusion effect incurred in the conventional technology.

摘要翻译： 提供半导体封装的镍/金（Ni / Au）焊盘结构及其制造方法。 制造方法包括制备芯层; 在芯层上形成导电迹线层; 图案化导电迹线层以形成至少一个导电迹线层的焊盘; 施加导电层; 形成光致抗蚀剂层以在所述焊盘上限定预定的镀覆区域，其中所述预定电镀区域的面积小于所述焊盘; 在预定的电镀区上形成Ni / Au层; 去除光致抗蚀剂层并蚀刻掉导电层; 以及施加焊接掩模层并在所述焊料掩模层中形成至少一个开口以露出所述焊盘，其中所述开口面积大于所述Ni / Au层。 通过上述方法制造的Ni / Au焊盘结构可以防止传统技术中引起的焊料挤出效应。

公开(公告)号：US20060053985A1

公开(公告)日：2006-03-16

申请号：US10940674

申请日：2004-09-15

申请人： Chien-Te Chen

发明人： Chien-Te Chen

IPC分类号： B25G1/01

CPC分类号： B25G1/00

摘要： A handle of a hand tool includes an enclosed chamber defined therein and a shank is connected to an end of the handle. The enclosed chamber allows the handle to be floatable in water. A fluorescent layer is coated on an outer periphery of the handle such that the handle can be seen in dark.

摘要翻译： 手工具的手柄包括限定在其中的封闭室，并且柄部连接到手柄的端部。 封闭的腔室允许手柄在水中漂浮。 荧光层被涂覆在手柄的外周上，使得可以在黑暗中看到手柄。

公开(公告)号：US20050247481A1

公开(公告)日：2005-11-10

申请号：US10935870

申请日：2004-09-07

申请人： Chien-Te Chen ,  Chih-Hao Chang

发明人： Chien-Te Chen ,  Chih-Hao Chang

IPC分类号： H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K3/24 ,  H05K3/40 ,  H05K3/46 ,  H05K10/00

CPC分类号： H05K1/0269 ,  H05K3/0052 ,  H05K3/242 ,  H05K3/403 ,  H05K3/4602 ,  H05K2201/0919 ,  H05K2201/09781 ,  H05K2203/163 ,  H05K2203/175 ,  Y10T29/49128

摘要： A circuit board with a quality-indicator mark and a method for indicating quality of the circuit board. The circuit board includes a plurality of circuit board units. A plating bus is formed around each circuit board unit and extended to form a plating trace in an inner-layer circuit structure of each circuit board unit. The inner-layer circuit structure is inspected in quality to maintain or break connection between the plating trace and plating bus if the quality is good or not. At least one circuit structure is formed on the inner-layer circuit structure and electrically connected to the plating trace to form a conductive mark on each circuit board unit. A metal protection layer is formed on the at least one circuit structure via the plating bus, and the conductive mark with the metal protection layer indicates that the inner-layer circuit structure of the circuit board unit is good.

摘要翻译： 具有质量指示标记的电路板和用于指示电路板的质量的方法。 电路板包括多个电路板单元。 在每个电路板单元周围形成电镀母线，并延伸以在每个电路板单元的内层电路结构中形成电镀痕迹。 如果质量好，内层电路结构的质量将被检查以维持或断开电镀痕迹和电镀母线之间的连接。 在内层电路结构上形成至少一个电路结构，并电连接到电镀迹线，以在每个电路板单元上形成导电标记。 金属保护层通过电镀母线形成在至少一个电路结构上，金属保护层的导电标记表示电路板单元的内层电路结构良好。

公开(公告)号：USD687692S1

公开(公告)日：2013-08-13

申请号：US29436779

申请日：2012-11-09

申请人： Chien-Te Chen

设计人： Chien-Te Chen

公开(公告)号：US07141868B2

公开(公告)日：2006-11-28

申请号：US11059143

申请日：2005-02-15

申请人： Yu-Lin Liao ,  Chien-Te Chen

发明人： Yu-Lin Liao ,  Chien-Te Chen

IPC分类号： H01L23/495

CPC分类号： H05K3/242 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49894 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2223/5442 ,  H01L2223/54473 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/181 ,  H05K3/0052 ,  H05K3/28 ,  H05K3/284 ,  H05K2201/09781 ,  H05K2201/0989 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/00012

摘要： A flash preventing substrate and a method for fabricating the same are proposed. A core defined with a plurality of substrate units is prepared. A circuit patterning process is performed to form circuit structures on the core corresponding to the substrate units, plating buses between the adjacent substrate units and electrically connected to the circuit structures, and a molding ring surrounding all the substrate units. The molding ring is located at a position predetermined for contacting the substrate with a mold. A solder mask layer covers the circuit structures, the plating buses and the molding ring, and is formed with a plurality of openings therein, such that predetermined portions of the circuit structures are exposed via the openings and serve as electrical input/output connections. During a molding process, the mold can tightly abut against the solder mask layer covering the molding ring to prevent outward flashes of an encapsulating material.

摘要翻译： 提出防闪光基板及其制造方法。 制备由多个基板单元限定的芯。 进行电路图案化处理，以在与基板单元相对应的芯上形成电路结构，在相邻的基板单元之间电镀总线并电连接到电路结构，以及围绕所有基板单元的模制环。 模制环位于预定的用于使基板与模具接触的位置。 焊接掩模层覆盖电路结构，电镀母线和成型环，并且在其中形成有多个开口，使得电路结构的预定部分经由开口暴露并用作电输入/输出连接。 在模制过程中，模具可以紧密地抵靠覆盖模制环的焊接掩模层，以防止封装材料向外闪烁。

公开(公告)号：US20060076695A1

公开(公告)日：2006-04-13

申请号：US11234652

申请日：2005-09-23

申请人： Wen-Chen Hsieh ,  Hsiu-Fang Chien ,  Chien-Te Chen

发明人： Wen-Chen Hsieh ,  Hsiu-Fang Chien ,  Chien-Te Chen

IPC分类号： H01L23/28

CPC分类号： H01L23/3121 ,  H01L21/565 ,  H01L21/566 ,  H01L2224/16 ,  H01L2224/83104 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2224/0401

摘要： A semiconductor package with flash-absorbing mechanism and a fabrication method thereof are proposed, wherein a flash-absorbing structure is formed on a gold-plated copper layer of a substrate, and adhesion between the flash-absorbing structure and a molding material is larger than that between the molding material and a mold, such that flashes of the molding material are not adhered to the mold after completing a molding process unlike the conventional technology, thereby ensuring quality of the fabricated semiconductor package.

摘要翻译： 提出了一种具有闪光吸收机构的半导体封装及其制造方法，其中在衬底的镀金铜层上形成闪光吸收结构，并且闪光吸收结构与成型材料之间的粘合力大于 在模制材料和模具之间，使得成型材料的闪光在完成模制工艺之后不会像传统技术那样粘附到模具上，从而确保制造的半导体封装的质量。

公开(公告)号：US20060060958A1

公开(公告)日：2006-03-23

申请号：US11222386

申请日：2005-09-07

申请人： Chien-Te Chen ,  Wen-Hsin Wang

发明人： Chien-Te Chen ,  Wen-Hsin Wang

IPC分类号： H01L23/48

CPC分类号： H05K1/114 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/181 ,  H05K1/113 ,  H05K3/3452 ,  H05K2201/0959 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package, and a fabrication method and a carrier thereof are provided. The fabrication method includes: preparing a core layer having a first surface and an opposed second surface, wherein the first and second surfaces are electrically connected to each other by a plurality of conductive vias; forming a plurality of bond pads on the second surface, wherein the bond pads are electrically connected to the conductive vias, and each of the conductive vias is partly located within a boundary of a corresponding one of the bond pads and is partly located out of the boundary of the corresponding bond pad, such that the carrier is fabricated; mounting and electrically connecting a chip to the first surface; forming an encapsulant on the first surface to encapsulate the chip; and forming solder joints on the bond pads of the second surface. By this arrangement, a popcorn effect is avoided.

摘要翻译： 提供半导体封装及其制造方法和载体。 制造方法包括：制备具有第一表面和相对的第二表面的芯层，其中第一表面和第二表面通过多个导电通孔彼此电连接; 在所述第二表面上形成多个接合焊盘，其中所述接合焊盘电连接到所述导电通孔，并且每个所述导电通孔部分地位于所述接合焊盘的对应的一个接合焊盘的边界内，并且部分地位于 边界，使得制造载体; 将芯片安装并电连接到第一表面; 在所述第一表面上形成密封剂以封装所述芯片; 以及在第二表面的接合焊盘上形成焊点。 通过这种安排，可以避免爆米花效应。