公开(公告)号：US5702984A

公开(公告)日：1997-12-30

申请号：US749124

申请日：1996-11-14

申请人： Claude Louis Bertin ,  Wayne John Howell ,  Erik Leigh Hedberg ,  Howard Leo Kalter ,  Gordon Arthur Kelley, Jr.

发明人： Claude Louis Bertin ,  Wayne John Howell ,  Erik Leigh Hedberg ,  Howard Leo Kalter ,  Gordon Arthur Kelley, Jr.

IPC分类号： H01L25/18 ,  G11C5/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/07 ,  H01L25/10 ,  H01L25/11 ,  H01L21/18

CPC分类号： G11C5/06 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40618 ,  G11C5/04 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4911 ,  H01L2224/85207 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06551 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/19041 ,  H01L2924/19107

摘要： An integrated multichip memory module structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the appearance of a single, higher level memory chip. A memory subunit is formed having N memory chips with each memory chip of the subunit having M memory devices. The controlling logic chip coordinates external communication with the N memory chips such that a single memory chip architecture with N.times.M memory devices appears at the module's I/O pins. A preformed electrical interface layer is employed at one end of the memory subunit to electrically interconnect the controlling logic chip with the memory chips comprising the subunit. The controlling logic chip has smaller dimensions than the dimensions of the memory chips comprising the subunit. A lead frame, having an inner opening extending therethrough, is secured to the electrical interface layer and the controlling logic chip is secured to the electrical interface layer so as to reside within the lead frame, thereby producing a dense multichip integrated circuit package. Corresponding fabrication techniques include an approach for facilitating metallization patterning on the side surface of the memory subunit.

摘要翻译： 一种集成多芯片存储器模块结构和制造方法，其中堆叠的半导体存储器芯片由控制逻辑芯片集成，使得以更高级别的存储器芯片的外观定义更强大的存储器架构。 形成具有N个存储器芯片的存储器子单元，该子单元的每个存储器芯片具有M个存储器件。 控制逻辑芯片协调与N个存储器芯片的外部通信，使得在模块的I / O引脚上出现具有NxM存储器件的单个存储器芯片架构。 在存储器子单元的一端采用预先形成的电接口层，以将控制逻辑芯片与包括该子单元的存储器芯片电互连。 控制逻辑芯片的尺寸小于包含子单元的存储器芯片的尺寸。 具有延伸穿过其中的内部开口的引线框固定到电接口层，并且控制逻辑芯片固定到电接口层以便驻留在引线框架内，从而产生致密的多芯片集成电路封装。 相应的制造技术包括促进存储器子单元的侧表面上的金属化图案化的方法。

公开(公告)号：US5946545A

公开(公告)日：1999-08-31

申请号：US942515

申请日：1997-10-02

申请人： Claude Louis Bertin ,  Erik Leigh Hedberg ,  Wayne John Howell

发明人： Claude Louis Bertin ,  Erik Leigh Hedberg ,  Wayne John Howell

IPC分类号： H01L21/66 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18 ,  G01R31/26 ,  H01L21/00

CPC分类号： H01L24/49 ,  G11C29/808 ,  H01L22/22 ,  H01L23/5382 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/4911 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06582 ,  H01L2225/06596 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/19107

摘要： Electronic semiconductor structures, and fabrication and sparing methods, each utilize an electrically programmable spare circuit incorporated with a multichip package. The programmable sparing capability in the multichip package is accomplished either with or without the inclusion of a spare chip(s). With a spare memory circuit, individual failed memory cells in the semiconductor chips of a stack can be functionally replaced by memory cells of the spare memory circuit subsequent to encapsulation and burn-in testing. With use of a spare chip, non-volatile sparing can occur subsequent to encapsulation and burn-in testing without physical rewiring of a wire bond connection. Specific details of alternate electronic semiconductor structures, and fabrication and sparing methods therefore, are set forth.

摘要翻译： 电子半导体结构以及制造和备用方法各自使用并入多芯片封装的电可编程备用电路。 多芯片封装中的可编程保护功能可以在有或没有包含备用芯片的情况下完成。 利用备用存储器电路，在封装和老化测试之后，堆叠的半导体芯片中的单个故障存储器单元可以在功能上被备用存储器电路的存储单元替代。 使用备用芯片，在封装和老化测试之后可能会发生非易失性保护，而无需线接合连接的物理重新布线。 因此，提出了替代电子半导体结构的具体细节，以及制造和备用方法。

公开(公告)号：US5798282A

公开(公告)日：1998-08-25

申请号：US429981

申请日：1995-04-27

申请人： Claude Louis Bertin ,  Erik Leigh Hedberg ,  Wayne John Howell

发明人： Claude Louis Bertin ,  Erik Leigh Hedberg ,  Wayne John Howell

IPC分类号： H01L21/66 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18 ,  H01L21/50

CPC分类号： H01L24/49 ,  G11C29/808 ,  H01L22/22 ,  H01L23/5382 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/4911 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06582 ,  H01L2225/06596 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/19107

摘要： Electronic semiconductor structures, and fabrication and sparing methods, each utilize an electrically programmable spare circuit incorporated with a multichip package. The programmable sparing capability in the multichip package is accomplished either with or without the inclusion of a spare chip(s). With a spare memory circuit, individual failed memory cells in the semiconductor chips of a stack can be functionally replaced by memory cells of the spare memory circuit subsequent to encapsulation and burn-in testing. With use of a spare chip, non-volatile sparing can occur subsequent to encapsulation and burn-in testing without physical rewiring of a wire bond connection. Specific details of alternate electronic semiconductor structures, and fabrication and sparing methods therefore, are set forth.

摘要翻译： 电子半导体结构以及制造和备用方法各自使用并入多芯片封装的电可编程备用电路。 多芯片封装中的可编程保护功能可以在有或没有包含备用芯片的情况下完成。 利用备用存储器电路，在封装和老化测试之后，堆叠的半导体芯片中的单个故障存储器单元可以在功能上被备用存储器电路的存储单元替代。 使用备用芯片，在封装和老化测试之后可能会发生非易失性保护，而无需线接合连接的物理重新布线。 因此，提出了替代电子半导体结构的具体细节，以及制造和备用方法。

公开(公告)号：US5648684A

公开(公告)日：1997-07-15

申请号：US506939

申请日：1995-07-26

申请人： Claude Louis Bertin ,  Wayne John Howell ,  Howard Leo Kalter

发明人： Claude Louis Bertin ,  Wayne John Howell ,  Howard Leo Kalter

IPC分类号： H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L23/02

CPC分类号： H01L25/0657 ,  H01L25/18 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/48145 ,  H01L2225/06506 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06586 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041

摘要： An endcap chip is provided for a multichip stack comprising multiple integrated circuit chips laminated together. The endcap chip has a substrate with an upper surface and a edge surface, which extends in a plane orthogonal to the upper surface. At least one conductive, monolithic L-connect is disposed over the substrate such that a first leg extends at least partially over the upper surface of the substrate and a second leg extends at least partially over the edge surface of the substrate. When the endcap chip is located at the end of the multichip stack, the at least one conductive, monolithic L-connect electrically connects metal on an end face of the stack to metal on a side face of the stack. A fabrication process is set forth for producing the endcap chip with lithographically defined dimensions.

摘要翻译： 提供了一种用于多芯片堆叠的端盖芯片，其包括层叠在一起的多个集成电路芯片。 端盖芯片具有上表面和边缘表面的基板，该基板在与上表面正交的平面中延伸。 至少一个导电的单片L形连接器设置在衬底上，使得第一腿部至少部分地延伸到衬底的上表面上，并且第二腿部至少部分地延伸到衬底的边缘表面上。 当端盖芯片位于多芯片堆叠的端部时，至少一个导电的单片L形连接器将堆叠的端面上的金属与堆叠的侧面上的金属电连接。 阐述了用于制造具有光刻尺寸的端盖芯片的制造工艺。

公开(公告)号：US5923181A

公开(公告)日：1999-07-13

申请号：US840041

申请日：1997-04-24

申请人： Kenneth Edward Beilstein, Jr. ,  Claude Louis Bertin ,  Dennis Charles Dubois ,  Wayne John Howell ,  Gordon Arthur Kelley, Jr. ,  Christopher Paul Miller ,  David Jacob Perlman ,  Gustav Schrottke ,  Edmund Juris Sprogis ,  Jody John VanHorn

发明人： Kenneth Edward Beilstein, Jr. ,  Claude Louis Bertin ,  Dennis Charles Dubois ,  Wayne John Howell ,  Gordon Arthur Kelley, Jr. ,  Christopher Paul Miller ,  David Jacob Perlman ,  Gustav Schrottke ,  Edmund Juris Sprogis ,  Jody John VanHorn

IPC分类号： G01R31/26 ,  G01R1/04 ,  G01R31/28 ,  H01L21/66 ,  H01L25/00 ,  G01R31/02

CPC分类号： G01R31/2863 ,  G01R1/0483 ,  G01R31/2851 ,  G01R31/2886 ,  G01R31/2889 ,  H01L2924/0002

摘要： Methods and apparatus are set forth for burn-in stressing and simultaneous testing of a plurality of semiconductor device chips laminated together in a stack configuration to define a multichip module. Testing is facilitated by connecting temporary interconnect wiring to an access surface of the multichip module. This temporary interconnect wiring electrically interconnects at least some semiconductor device chips within the module. Prior to burn-in stressing and testing, a separate electrical screening step occurs to identify any electrical defect in the connection between the temporary interconnect wiring and the multichip module. If an electrical defect is identified, various techniques for removing or isolating the defect are presented. Thereafter, burn-in stressing and simultaneous testing of the semiconductor chips within the multichip module occurs using the temporary interconnect wiring. Various alignment and test fixtures are described for facilitating this burn-in and simultaneous testing of the semiconductor chips within the multichip module.

摘要翻译： 阐述了以堆叠配置层叠在一起的多个半导体器件芯片的老化应力和同时测试方法和装置，以限定多芯片模块。 通过将临时互连线连接到多芯片模块的访问表面来实现测试。 该临时互连布线使模块内的至少一些半导体器件芯片电互连。 在老化应力和测试之前，会发生单独的电气筛选步骤，以识别临时互连线路和多芯片模块之间的连接中的任何电气缺陷。 如果识别出电气缺陷，则提出了用于去除或隔离缺陷的各种技术。 此后，使用临时互连线路进行多芯片模块内的半导体芯片的老化强度和同时测试。 描述了各种对准和测试夹具，以便于该多芯片模块内的半导体芯片的老化和同时测试。

公开(公告)号：US5686843A

公开(公告)日：1997-11-11

申请号：US497126

申请日：1995-06-30

申请人： Kenneth Edward Beilstein, Jr. ,  Claude Louis Bertin ,  Dennis Charles Dubois ,  Wayne John Howell ,  Gordon Arthur Kelley, Jr. ,  Christopher Paul Miller ,  David Jacob Perlman ,  Gustav Schrottke ,  Edmund Juris Sprogis ,  Jody John VanHorn

发明人： Kenneth Edward Beilstein, Jr. ,  Claude Louis Bertin ,  Dennis Charles Dubois ,  Wayne John Howell ,  Gordon Arthur Kelley, Jr. ,  Christopher Paul Miller ,  David Jacob Perlman ,  Gustav Schrottke ,  Edmund Juris Sprogis ,  Jody John VanHorn

IPC分类号： G01R31/26 ,  G01R1/04 ,  G01R31/28 ,  H01L21/66 ,  H01L25/00 ,  G01R31/02

CPC分类号： G01R31/2863 ,  G01R1/0483 ,  G01R31/2851 ,  G01R31/2886 ,  G01R31/2889 ,  H01L2924/0002

摘要： Methods and apparatus are set forth for burn-in stressing and simultaneous testing of a plurality of semiconductor device chips laminated together in a stack configuration to define a multichip module. Testing is facilitated by connecting temporary interconnect wiring to an access surface of the multichip module. This temporary interconnect wiring electrically interconnects at least some semiconductor device chips within the module. Prior to burn-in stressing and testing, a separate electrical screening step occurs to identify any electrical defect in the connection between the temporary interconnect wiring and the multichip module. If an electrical defect is identified, various techniques for removing or isolating the defect are presented. Thereafter, burn-in stressing and simultaneous testing of the semiconductor chips within the multichip module occurs using the temporary interconnect wiring. Various alignment and test fixtures are described for facilitating this burn-in and simultaneous testing of the semiconductor chips within the multichip module.

摘要翻译： 阐述了以堆叠配置层叠在一起的多个半导体器件芯片的老化应力和同时测试方法和装置，以限定多芯片模块。 通过将临时互连线连接到多芯片模块的访问表面来实现测试。 该临时互连布线使模块内的至少一些半导体器件芯片电互连。 在老化应力和测试之前，会发生单独的电气筛选步骤，以识别临时互连线路和多芯片模块之间的连接中的任何电气缺陷。 如果识别出电气缺陷，则提出了用于去除或隔离缺陷的各种技术。 此后，使用临时互连布线发生多芯片模块内的半导体芯片的老化强度和同时测试。 描述了各种对准和测试夹具，以便于该多芯片模块内的半导体芯片的老化和同时测试。

公开(公告)号：US5925924A

公开(公告)日：1999-07-20

申请号：US843177

申请日：1997-04-14

申请人： John Edward Cronin ,  Wayne John Howell ,  Howard Leo Kalter ,  Patricia Ellen Marmillion ,  Anthony Palagonia ,  Bernadette Ann Pierson ,  Dennis Arthur Schmidt

发明人： John Edward Cronin ,  Wayne John Howell ,  Howard Leo Kalter ,  Patricia Ellen Marmillion ,  Anthony Palagonia ,  Bernadette Ann Pierson ,  Dennis Arthur Schmidt

IPC分类号： H01L21/304 ,  H01L21/301 ,  H01L21/78 ,  H01L21/98 ,  H01L25/065 ,  H01L29/06

CPC分类号： H01L25/50 ,  H01L21/78 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2924/10253 ,  Y10S148/028 ,  Y10S438/977

摘要： Integrated Circuit ("IC") chips are formed with precisely defined edges and sizing. At the wafer processing level, trenches are lithographically etched in the kerf regions to define the edges of the IC chips on the wafer. The trenches are filled with insulating material, and upper level wiring and metallization is completed for the IC chips on the wafer. Further trenches are defined down to the filled previously formed trenches. The wafer is thinned from its bottom up to the filled trenches, and the insulating material therein is removed to separate the individual IC chips from the wafer. The precision of IC chip edge definition facilitates forming the IC chips into stacks more easily because many stack level alignment processes become unnecessary.

摘要翻译： 集成电路（“IC”）芯片具有精确定义的边缘和尺寸。 在晶片处理级别，在切口区域中光刻地蚀刻沟槽，以限定晶片上的IC芯片的边缘。 沟槽填充有绝缘材料，并且晶片上的IC芯片完成了上层布线和金属化。 另外的沟槽被定义为填充的先前形成的沟槽。 将晶片从其底部减薄到填充的沟槽，并且去除其中的绝缘材料以将各个IC芯片与晶片分离。 IC芯片边缘定义的精度有助于将IC芯片更容易地堆叠成堆栈，因为不需要许多堆叠级对准过程。

公开(公告)号：US5691248A

公开(公告)日：1997-11-25

申请号：US507186

申请日：1995-07-26

申请人： John Edward Cronin ,  Wayne John Howell ,  Howard Leo Kalter ,  Patricia Ellen Marmillion ,  Anthony Palagonia ,  Bernadette Ann Pierson ,  Dennis Arthur Schmidt

发明人： John Edward Cronin ,  Wayne John Howell ,  Howard Leo Kalter ,  Patricia Ellen Marmillion ,  Anthony Palagonia ,  Bernadette Ann Pierson ,  Dennis Arthur Schmidt

IPC分类号： H01L21/304 ,  H01L21/301 ,  H01L21/78 ,  H01L21/98 ,  H01L25/065 ,  H01L21/302

CPC分类号： H01L25/50 ,  H01L21/78 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2924/10253 ,  Y10S148/028 ,  Y10S438/977

摘要： Integrated Circuit ("IC") chips are formed with precisely defined edges and sizing. At the wafer processing level, trenches are lithographically etched in the kerf regions to define the edges of the IC chips on the wafer. The trenches are filled with insulating material, and upper level wiring and metallization is completed for the IC chips on the wafer. Further trenches are defined down to the filled previously formed trenches. The wafer is thinned from its bottom up to the filled trenches, and the insulating material therein is removed to separate the individual IC chips from the wafer. The precision of IC chip edge definition facilitates forming the IC chips into stacks more easily because many stack level alignment processes become unnecessary.

摘要翻译： 集成电路（“IC”）芯片具有精确定义的边缘和尺寸。 在晶片处理级别，在切口区域中光刻地蚀刻沟槽，以限定晶片上的IC芯片的边缘。 沟槽填充有绝缘材料，并且晶片上的IC芯片完成了上层布线和金属化。 另外的沟槽被定义为填充的先前形成的沟槽。 将晶片从其底部减薄到填充的沟槽，并且去除其中的绝缘材料以将各个IC芯片与晶片分离。 IC芯片边缘定义的精度有助于将IC芯片更容易地堆叠成堆栈，因为不需要许多堆叠级对准过程。

公开(公告)号：US06455778B2

公开(公告)日：2002-09-24

申请号：US09894692

申请日：2001-06-28

申请人： Claude Louis Bertin ,  Thomas George Ference ,  Wayne John Howell ,  John Atkinson Fifield

发明人： Claude Louis Bertin ,  Thomas George Ference ,  Wayne John Howell ,  John Atkinson Fifield

IPC分类号： H01L3300

CPC分类号： H01L23/49816 ,  H01L23/49524 ,  H01L23/49531 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06579 ,  H01L2924/00013 ,  H01L2924/01079 ,  H01L2924/07811 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0228 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2924/00012

摘要： Thin-film microflex twisted-wire pair and other connectors are disclosed. Semiconductor packages include microflex technology that electrically connects at least one chip to another level of packaging. Microflex connectors, such as thin-film twisted-wire pair connectors according to the present invention provide superior electrical performance, which includes reduced line inductance, incorporation of integrated passive components, and attachment of discrete passive and active components to the microflex. All of these features enable operation of the chip at increased frequencies.

公开(公告)号：US5907178A

公开(公告)日：1999-05-25

申请号：US031028

申请日：1998-02-26

申请人： Robert Grover Baker ,  Claude Louis Bertin ,  Wayne John Howell ,  Joseph Michael Mosley

发明人： Robert Grover Baker ,  Claude Louis Bertin ,  Wayne John Howell ,  Joseph Michael Mosley

IPC分类号： H01L27/14 ,  G01J1/02 ,  H01L21/60 ,  H01L23/02 ,  H01L25/065 ,  H01L23/34

CPC分类号： H01L25/065 ,  H01L25/0652 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2225/06551 ,  H01L2924/01077 ,  H01L2924/16152

摘要： An electronic module includes multiple stacked bare IC chips ("a stack") and a sensor assembly that is mechanically coupled to an end surface of the stack. Electrical connection between the sensor assembly and the stack is provided by a metallization layer disposed on a side-surface of the stack. Specifically, wiring of the sensor assembly extends to an edge surface thereof corresponding to the side-surface of the stack where it electrically connects to the side-surface wiring. The IC chips of the stack are similarly electrically connected to the side-surface wiring. Multiple sensors (e.g., CCD arrays) may be electrically and mechanically coupled to multiple surfaces of the stack for providing a, e.g., multi-view imaging module. Multiple electrical and mechanical options exist for the connection of sensors to stacks within electronic modules.

摘要翻译： 电子模块包括多个堆叠的裸IC芯片（“堆叠”）和机械耦合到堆叠的端表面的传感器组件。 传感器组件和堆叠之间的电连接由设置在堆叠的侧表面上的金属化层提供。 具体地说，传感器组件的布线延伸到与其电连接到侧面布线的堆叠的侧表面相对应的边缘表面。 堆叠的IC芯片类似地电连接到侧面布线。 多个传感器（例如，CCD阵列）可以电和机械耦合到堆叠的多个表面以提供例如多视图成像模块。 存在多种电气和机械选项，用于将传感器连接到电子模块内的堆叠。