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27 条记录 (耗时 0.031 秒)

    Circuitized structures produced by the methods of electroless plating
    1.
    发明授权
    Circuitized structures produced by the methods of electroless plating 失效
    通过无电镀方法生产的电路结构

    公开(公告)号：US06680440B1

    公开(公告)日：2004-01-20

    申请号：US09027856

    申请日：1998-02-23

    申请人： David John Russell ,  Gerald Walter Jones ,  Heike Marcello ,  Voya Rista Markovich

    发明人： David John Russell ,  Gerald Walter Jones ,  Heike Marcello ,  Voya Rista Markovich

    IPC分类号： H05K116

    CPC分类号： H05K3/287 ,  G03F7/0385 ,  H05K3/0023 ,  H05K3/184 ,  H05K3/243 ,  H05K2203/072

    摘要： The present invention provides new methods for electroless plating of metal particularly gold and copper onto substrates, such as circuitized substrates, which reduces processing steps, reduces metal consumption, and reduces the scraping of parts due to contamination. The method employs a permanent plating resist. The method for electrolessly plating metal onto a substrate, including the following steps: providing: an uncured, photoimagable, dielectric permanent plating resist comprising: from about 10 to 80% of phenoxy polyol resin which is the condensation product of epichlorohydrin and bisphenol A, having a molecular weight of from about 40,000 to 130,000; from about 20 to 90% of an epoxidized multifunctional bisphenol A formaldehyde novolac resin having a molecular weight of from about 4,000 to 10,000; from 0 to 50% of a diglycidyl ether of bisphenol A having a molecular weight of from about 600 to 2,500; and from about 0.1 to 15 parts by weight of the total resin weight, a cationic photoinitiator; applying the permanent plating resist on the substrate; photopatterning the permanent plating resist to form apertures therein which expose areas of the substrate; and electrolessly plating metal onto the exposed areas of the substrate. The permanent plating resist is useful to protect the substrate areas including for example metallized features on the substrate, from the electroless deposition of metal during electroless plating; thus selective plating of metal is achieved. The permanent plating resist is not degraded by conventional gold or copper electroless baths. The invention also relates to circuitized structures produced by the methods of electroless plating.

    摘要翻译： 本发明提供了金属特别是金和铜在电路化基板等基板上进行化学镀的新方法，其减少了加工步骤，降低了金属消耗，并减少了由于污染引起的部件刮擦。 该方法采用永久电镀抗蚀剂。 将金属无电镀在基板上的方法，包括以下步骤：提供：未固化的，可光成像的绝缘永久电镀抗蚀剂，其包含：约10至80％的作为表氯醇和双酚A的缩合产物的苯氧基多元醇树脂，其具有 分子量为约40,000至130,000; 约20至90％的分子量为约4,000至10,000的环氧化多官能双酚A甲醛酚醛清漆树脂; 0至50％的分子量为约600至2,500的双酚A的二缩水甘油醚; 和约0.1至15重量份的总树脂重量，阳离子光引发剂; 在基板上施加永久电镀抗蚀剂; 对永久电镀抗蚀剂进行光图案化以在其中形成露出基板的区域的孔; 并将金属化学镀在衬底的暴露区域上。 永久电镀抗蚀剂可用于保护衬底区域，包括例如基板上的金属化特征，在化学镀期间的金属化学沉积; 从而实现了金属的选择性镀覆。 永久电镀抗蚀剂不会被常规的金或铜无电镀浴降解。 本发明还涉及通过化学镀方法制造的电路结构。

    Modular circuit package having vertically aligned power and signal cores
    7.
    发明授权
    Modular circuit package having vertically aligned power and signal cores 失效
    具有垂直对齐的功率和信号核心的模块化电路封装

    公开(公告)号：US5876842A

    公开(公告)日：1999-03-02

    申请号：US774849

    申请日：1996-12-27

    申请人： Thomas Patrick Duffy ,  Harold Kohn ,  Voya Rista Markovich ,  David John Russell

    发明人： Thomas Patrick Duffy ,  Harold Kohn ,  Voya Rista Markovich ,  David John Russell

    IPC分类号： H01L23/498 ,  H01L23/50 ,  H05K1/11 ,  H05K3/00 ,  H05K3/42 ,  H05K3/46 ,  B32B9/00

    CPC分类号： H05K3/4641 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/50 ,  H05K1/113 ,  H05K3/429 ,  H01L2224/16225 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10734 ,  H05K3/0094 ,  H05K3/4623 ,  Y10S428/901 ,  Y10T428/24917

    摘要： A modular structure for providing electrical interconnections achieves greatly increased wiring density by forming vias and wiring patterns by chemical (e.g. lithographic) processes rather than by mechanical processes such as punching of vias and screening patterns of conductive paste. A basic module is a power core comprising an apertured metallic foil with an insulator applied to surfaces thereof, extending through at least one aperture and exposing the metallic foil in at least one aperture. The foil in the power core provides stiffness to facilitate subsequent handling and electrical shielding between conductive layers as well as a potential power connection. Via connections of increased conductivity and robustness are formed by plating the interior of vias after lamination of a desired combination of power cores and signal cores. Vias remain unfilled until after lamination and are available to facilitate optical alignment of composite layers including signal cores, power cores and laminated combinations thereof.

    摘要翻译： 用于提供电互连的模块化结构通过通过化学（例如平版印刷）工艺形成通孔和布线图案而不是通过机械工艺例如穿孔和导电浆料的筛选图案来实现大大增加布线密度。 基本模块是功率芯，其包括具有施加到其表面的绝缘体的多孔金属箔，延伸穿过至少一个孔并且在至少一个孔中暴露金属箔。 动力芯中的箔片提供刚度以便于导电层之间的后续处理和电屏蔽以及潜在的电力连接。 通过在层叠所需的功率核心和信号芯组合之后，通过对通孔内部进行电镀而形成通过增加导电性和鲁棒性的连接。 在层压之后，通孔保持未填充，并且可用于促进复合层的光学对准，包括信号芯，功率芯及其层叠组合。

    Process for high resolution photoimageable dielectric
    9.
    发明授权
    Process for high resolution photoimageable dielectric 失效
    高分辨率可光成像电介质的工艺

    公开(公告)号：US6022670A

    公开(公告)日：2000-02-08

    申请号：US48753

    申请日：1998-03-26

    申请人： David John Russell ,  Donald Herman Glatzel

    发明人： David John Russell ,  Donald Herman Glatzel

    IPC分类号： H01L21/48 ,  H01L23/498 ,  H05K3/00 ,  H05K3/46 ,  G03F7/00

    CPC分类号： H05K3/4661 ,  H01L21/4857 ,  H01L23/49894 ,  H01L2924/0002 ,  H05K2203/1152 ,  H05K3/0023

    摘要： A novel process for circuitizing a dielectric layer, particularly for adding wiring planes, which is employed in the fabrication of circuitized structures, that does not requiring drilling of vias, yet provides good adhesion of circuitization to dielectric layer. In its broadest sense the method comprises the following steps: a. providing: a substrate; a hydrophobic, uncured, photoimagable, dielectric film having a solvent content of from about 5 to 30%; metal foil; b. contacting the metal foil and the dielectric film so that a replicate image is formed in the dielectric film; c. disposing the dielectric film on the substrate either after step a or step b; d. etching the metal foil from the dielectric film after step c; e. after step d, photoimaging the dielectric film to form vias or through holes in the dielectric film; and then metallizing the film after step e, to provide circuitization atop the dielectric film. The invention also relates to the circuitized structures produce by the method.

    摘要翻译： 一种用于电路化电介质层的新颖方法，特别是用于添加用于制造电路化结构的布线平面的电介质层，其不需要钻孔，而是提供电介质层的良好粘合性。 在最广泛的意义上，该方法包括以下步骤：a。 提供：基材; 疏水的，未固化的，可光成像的介电膜，其溶剂含量为约5至30％; 金属箔 b。 使金属箔和电介质膜接触，使得在电介质膜中形成复制图像; C。 在步骤a或步骤b之后将电介质膜设置在衬底上; d。 在步骤c之后从电介质膜上蚀刻金属箔; e。 在步骤d之后，对电介质膜进行光成像以在电介质膜中形成通孔或通孔; 然后在步骤e之后对膜进行金属化，以在电介质膜的顶部提供电路。 本发明还涉及通过该方法产生的电路化结构。