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    GRAPHENE DEPOSITION
    1.
    发明申请
    GRAPHENE DEPOSITION 审中-公开
    石墨沉积

    公开(公告)号：US20110303899A1

    公开(公告)日：2011-12-15

    申请号：US13158186

    申请日：2011-06-10

    申请人： Deenesh Padhi ,  Jacob Janzen ,  Shahid Shaikh ,  Bok Hoen Kim ,  Barry Chin

    发明人： Deenesh Padhi ,  Jacob Janzen ,  Shahid Shaikh ,  Bok Hoen Kim ,  Barry Chin

    IPC分类号： H01L21/20 ,  H01L29/16

    CPC分类号： H01L21/0262 ,  H01J37/32091 ,  H01L21/02425 ,  H01L21/02491 ,  H01L21/02502 ,  H01L21/02527 ,  H01L23/373 ,  H01L29/66742 ,  H01L29/78684 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Embodiments of the invention are directed toward the deposition of Graphene on a semiconductor substrate. In some embodiments, these processes can occur at low temperature levels during a back end of the line process. For example, Graphene can be deposited in a CVD reactor at a processing temperature that is below 600° C. to protect previously deposited layers that may be susceptible to sustained higher temperatures. Graphene deposition can include the deposition of an underlayer (e.g., cobalt) followed by the flow of a carbon precursor (e.g., acetylene) at the processing temperature. Graphene can then be synthesized with during cooling, an RTP cure, and/or a UV cure.

    摘要翻译： 本发明的实施方案涉及在半导体衬底上沉积石墨烯。 在一些实施例中，这些过程可以在线路过程的后端期间以低温水平发生。 例如，石墨烯可以在低于600℃的处理温度下沉积在CVD反应器中，以保护可能易受持续较高温度影响的预先沉积的层。 石墨烯沉积可以包括在加工温度下沉积底层（例如钴），然后沉积碳前体（例如乙炔）。 然后可以在冷却，RTP固化和/或UV固化期间合成石墨烯。

    Damage-free sculptured coating deposition
    2.
    发明申请
    Damage-free sculptured coating deposition 审中-公开
    无损伤雕刻涂层沉积

    公开(公告)号：US20070178682A1

    公开(公告)日：2007-08-02

    申请号：US11733671

    申请日：2007-04-10

    申请人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen Chen ,  Barry Chin ,  Gene Kohara ,  Zheng Xu ,  Hong Zhang

    发明人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen Chen ,  Barry Chin ,  Gene Kohara ,  Zheng Xu ,  Hong Zhang

    IPC分类号： H01L21/20

    CPC分类号： H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

    摘要： We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer, said method comprising the steps of: a) applying a first portion of a sculptured layer with sufficiently low substrate bias that a surface onto which said sculptured layer is applied is not eroded away or contaminated in an amount which is harmful to said semiconductor device performance or longevity; and b) applying a subsequent portion of said sculptured layer with sufficiently high substrate bias to sculpture a shape from said the first portion, while depositing additional layer material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces and is especially helpful when the conductive layer is copper. In the application of a barrier layer, a first portion of barrier layer material is deposited on the substrate surface using standard sputtering techniques or using an ion deposition plasma, but in combination with sufficiently low substrate bias voltage (including at no applied substrate voltage) that the surfaces impacted by ions are not sputtered in an amount which is harmful to device performance or longevity. Subsequently, a second portion of barrier material is applied using ion deposition sputtering at increased substrate bias voltage which causes resputtering (sculpturing) of the first portion of barrier layer material, while enabling a more anisotropic deposition of newly depositing material. A conductive material, and particularly a copper seed layer applied to the feature may be accomplished using the same sculpturing technique as that described above with reference to the barrier layer.

    摘要翻译： 我们公开了使用离子沉积溅射在半导体特征表面上施加雕刻层的材料的方法，其中施加有雕刻层的表面被保护以通过冲击沉积层的离子来抵抗侵蚀和污染，所述方法包括 步骤：a）以足够低的衬底偏压施加雕刻层的第一部分，使得施加所述雕刻层的表面不会以对所述半导体器件的性能或寿命有害的量被侵蚀或污染; 以及b）将所述雕刻层的后续部分施加足够高的衬底偏压，以从所述第一部分雕刻形状，同时沉积附加层材料。 该方法特别适用于在半导体特征表面上雕刻阻挡层，润湿层和导电层，并且当导电层是铜时尤其有用。 在施加阻挡层时，使用标准溅射技术或使用离子沉积等离子体将阻挡层材料的第一部分沉积在衬底表面上，但是与足够低的衬底偏置电压（包括没有施加的衬底电压）组合， 受离子影响的表面不会以对器件性能或寿命有害的量溅射。 随后，使用离子沉积溅射在增加的衬底偏置电压下施加阻挡材料的第二部分，这导致阻挡层材料的第一部分的再溅射（雕刻），同时能够进行更多的各向异性沉积新沉积的材料。 应用于特征的导电材料，特别是铜种子层可以使用与上述参考阻挡层所述相同的雕刻技术来实现。

    Method of depositing a diffusion barrier layer and a metal conductive layer
    4.
    发明申请
    Method of depositing a diffusion barrier layer and a metal conductive layer 审中-公开
    沉积扩散阻挡层和金属导电层的方法

    公开(公告)号：US20050020080A1

    公开(公告)日：2005-01-27

    申请号：US10922052

    申请日：2004-08-18

    申请人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen Chen ,  Barry Chin ,  Gene Kohara ,  Zheng Xu ,  Hong Zhang

    发明人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen Chen ,  Barry Chin ,  Gene Kohara ,  Zheng Xu ,  Hong Zhang

    IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/4763 ,  H01L21/302 ,  H01L21/461

    CPC分类号： H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

    摘要： We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer, said method comprising the steps of: a) applying a first portion of a sculptured layer with sufficiently low substrate bias that a surface onto which said sculptured layer is applied is not eroded away or contaminated in an amount which is harmful to said semiconductor device performance or longevity; and b) applying a subsequent portion of said sculptured layer with sufficiently high substrate bias to sculpture a shape from said the first portion, while depositing additional layer material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces and is especially helpful when the conductive layer is copper. In the application of a barrier layer, a first portion of barrier layer material is deposited on the substrate surface using standard sputtering techniques or using all ion deposition plasma, but in combination with sufficiently low substrate bias voltage (including at no applied substrate voltage) that the surfaces impacted by ions are not sputtered in an amount which is harmful to device performance or longevity. Subsequently, a second portion of barrier material is applied using ion deposition sputtering at increased substrate bias voltage which causes resputtering (sculpturing) or the first portion of barrier layer material, while enabling a more anisotropic deposition of newly depositing material. A conductive material, and particularly a copper seed layer applied to the feature may be accomplished using the same sculpturing technique as that described above with reference to the barrier layer.

    摘要翻译： 我们公开了使用离子沉积溅射在半导体特征表面上施加雕刻层的材料的方法，其中施加有雕刻层的表面被保护以通过冲击沉积层的离子来抵抗侵蚀和污染，所述方法包括 步骤：a）以足够低的衬底偏压施加雕刻层的第一部分，使得施加所述雕刻层的表面不会以对所述半导体器件的性能或寿命有害的量被侵蚀或污染; 以及b）将所述雕刻层的后续部分施加足够高的衬底偏压，以从所述第一部分雕刻形状，同时沉积附加层材料。 该方法特别适用于在半导体特征表面上雕刻阻挡层，润湿层和导电层，并且当导电层是铜时尤其有用。 在施加阻挡层时，使用标准溅射技术或使用所有离子沉积等离子体将阻挡层材料的第一部分沉积在衬底表面上，但是与足够低的衬底偏置电压（包括没有施加的衬底电压）相结合， 受离子影响的表面不会以对器件性能或寿命有害的量溅射。 随后，使用离子沉积溅射以增加的衬底偏置电压施加阻挡材料的第二部分，其引起再溅射（雕刻）或阻挡层材料的第一部分，同时能够进行更多的各向异性沉积新沉积材料。 应用于特征的导电材料，特别是铜种子层可以使用与上述参考阻挡层所述相同的雕刻技术来实现。

    Ionized metal plasma Ta, TaNx, W, and WNx liners for gate electrode applications
    5.
    发明授权
    Ionized metal plasma Ta, TaNx, W, and WNx liners for gate electrode applications 失效
    用于栅电极应用的离子化金属等离子体Ta，TaNx，W和WNx衬垫

    公开(公告)号：US06313033B1

    公开(公告)日：2001-11-06

    申请号：US09362923

    申请日：1999-07-27

    申请人： Tony Chiang ,  Bingxi Sun ,  Suraj Rengarajan ,  Peijun Ding ,  Barry Chin

    发明人： Tony Chiang ,  Bingxi Sun ,  Suraj Rengarajan ,  Peijun Ding ,  Barry Chin

    IPC分类号： H01L2144

    CPC分类号： H01L27/1087 ,  H01L21/2855 ,  H01L21/76843 ,  H01L28/40 ,  H01L28/56 ,  H01L28/75

    摘要： The invention provides a method for forming a microelectronic device comprising: forming a first electrode; depositing an adhesion layer over the first electrode utilizing high density plasma physical vapor deposition, wherein the adhesion layer comprises a material selected from Ta, TaNx, W, WNx, Ta/TaNx, W/WNx, and combinations thereof, depositing a dielectric layer over the adhesion layer; and forming a second electrode over the dielectric layer. The invention also provides a microelectronic device comprising: a first electrode; a second electrode; a dielectric layer disposed between the first and second electrodes; and an adhesion layer disposed between the first electrode and the dielectric layer, wherein the adhesion layer comprises a material selected from Ta, TaNx, W, WNx, Ta/TaNx, W/WNx, and combinations thereof.

    摘要翻译： 本发明提供一种形成微电子器件的方法，包括：形成第一电极; 使用高密度等离子体物理气相沉积在第一电极上沉积粘合层，其中粘合层包括选自Ta，TaNx，W，WNx，Ta / TaNx，W / WNx的材料及其组合，将介电层沉积在 粘合层; 以及在所述电介质层上形成第二电极。 本发明还提供了一种微电子器件，包括：第一电极; 第二电极; 设置在所述第一和第二电极之间的电介质层; 以及设置在第一电极和电介质层之间的粘合层，其中粘合层包括选自Ta，TaNx，W，WNx，Ta / TaNx，W / WNx的材料及其组合。

    Copper alloy seed layer for copper metallization in an integrated circuit
    6.
    发明授权
    Copper alloy seed layer for copper metallization in an integrated circuit 失效
    铜合金种子层用于集成电路中的铜金属化

    公开(公告)号：US06066892A

    公开(公告)日：2000-05-23

    申请号：US79107

    申请日：1998-05-14

    申请人： Peijun Ding ,  Tony Chiang ,  Imran Hashim ,  Bingxi Sun ,  Barry Chin

    发明人： Peijun Ding ,  Tony Chiang ,  Imran Hashim ,  Bingxi Sun ,  Barry Chin

    IPC分类号： H01L21/28 ,  C23C14/02 ,  C23C14/16 ,  C23C16/02 ,  C23C16/06 ,  H01L21/203 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L29/45

    CPC分类号： H01L21/76843 ,  C23C14/024 ,  C23C14/025 ,  C23C14/16 ,  C23C14/165 ,  C23C16/0281 ,  C23C16/06 ,  H01L21/28556 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76867 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76888 ,  H01L23/53233 ,  H01L23/53238 ,  H01L21/2855 ,  H01L2924/0002

    摘要： A copper metallization structure in which a layer of a copper alloy, such as Cu--Mg or Cu--Al is deposited over a silicon oxide based dielectric layer and a substantially pure copper layer is deposited over the copper alloy layer. The copper alloy layer serves as a seed or wetting layer for subsequent filling of via holes and trenches with substantially pure copper. Preferred examples of the alloying elements and their atomic alloying percentage include magnesium between 0.05 and 6% and aluminum between 0.05 and 0.3%. Further examples include boron, tantalum, tellurium, and titanium. Preferably, the copper alloy is deposited cold in a sputter process, but, during the deposition of the pure copper layer or afterwards in a separate annealing step, the temperature is raised sufficiently high to cause the alloying element of the copper alloy to migrate to the dielectric layer and form a barrier there against diffusion of copper into and through the dielectric layer. This barrier also promotes adhesion of the alloy layer to the dielectric layer, thereby forming a superior wetting and seed layer for subsequent copper full-fill techniques. Filling of the alloy-lined feature can be accomplished using PVD, CVD, or electro/electroless plating.

    摘要翻译： 在铜合金层上沉积铜基金属化结构，其中在氧化硅基介电层和基本上纯的铜层上沉积诸如Cu-Mg或Cu-Al的铜合金层。 铜合金层用作种子或润湿层，用于随后用基本上纯的铜填充通孔和沟槽。 合金元素的优选实例及其原子合金化百分比包括0.05至6％的镁和0.05-0.3％的铝。 其他实例包括硼，钽，碲和钛。 优选地，铜合金在溅射过程中冷沉积，但是在纯铜层沉积期间或之后在单独的退火步骤中，温度升高到足够高以使铜合金的合金元素迁移到 电介质层，并形成阻挡铜，以扩散到介电层中并穿过介电层。 该屏障还促进了合金层对电介质层的粘附，从而形成了用于随后的铜全填充技术的优异的润湿和种子层。 可以使用PVD，CVD或电/无电镀来完成合金衬里特征的填充。

    Method of depositing a metal seed layer on semiconductor substrates
    10.
    发明申请
    Method of depositing a metal seed layer on semiconductor substrates 失效
    在半导体衬底上沉积金属种子层的方法

    公开(公告)号：US20050085068A1

    公开(公告)日：2005-04-21

    申请号：US10981319

    申请日：2004-11-03

    申请人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen Chen ,  Barry Chin ,  Gene Kohara ,  Zheng Xu ,  Hong Zhang

    发明人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen Chen ,  Barry Chin ,  Gene Kohara ,  Zheng Xu ,  Hong Zhang

    IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/4763

    CPC分类号： H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

    摘要： We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer, said method comprising the steps of a) applying a first portion of a sculptured layer with sufficiently low substrate bias that a surface onto which said sculptured layer is applied is not eroded away or contaminated in an amount which is harmful to said semiconductor device performance or longevity; and b) applying a subsequent portion of said sculptured layer with sufficiently high substrate bias to sculpture a shape from said the first portion, while depositing additional layer material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces and is especially helpful when the conductive layer is copper. In the application of a barrier layer, a first portion of barrier layer material is deposited on the substrate surface using standard sputtering techniques or using an ion deposition plasma, but in combination with sufficiently low substrate bias voltage (including at no applied substrate voltage) that the surfaces impacted by ions are not sputtered in an amount which is harmful to device performance or longevity. Subsequently, a second portion of barrier material is applied using ion deposition sputtering at increased substrate bias voltage which causes resputtering (sculpturing) of the first portion of barrier layer material, while enabling a more anisotropic deposition of newly depositing material. A conductive material, and particularly a copper seed layer applied to the feature may be accomplished using the same sculpturing technique as that described above with reference to the barrier layer.

    摘要翻译： 我们公开了使用离子沉积溅射在半导体特征表面上施加雕刻层的材料的方法，其中施加有雕刻层的表面被保护以通过冲击沉积层的离子来抵抗侵蚀和污染，所述方法包括 步骤：a）以足够低的衬底偏压施加雕刻层的第一部分，使得施加所述雕刻层的表面不会以对所述半导体器件的性能或寿命有害的量被腐蚀掉或污染; 以及b）将所述雕刻层的后续部分施加足够高的衬底偏压，以从所述第一部分雕刻形状，同时沉积附加层材料。 该方法特别适用于在半导体特征表面上雕刻阻挡层，润湿层和导电层，并且当导电层是铜时尤其有用。 在施加阻挡层时，使用标准溅射技术或使用离子沉积等离子体将阻挡层材料的第一部分沉积在衬底表面上，但是与足够低的衬底偏置电压（包括没有施加的衬底电压）组合， 受离子影响的表面不会以对器件性能或寿命有害的量溅射。 随后，使用离子沉积溅射在增加的衬底偏置电压下施加阻挡材料的第二部分，这导致阻挡层材料的第一部分的再溅射（雕刻），同时能够进行更多的各向异性沉积新沉积的材料。 应用于特征的导电材料，特别是铜种子层可以使用与上述参考阻挡层所述相同的雕刻技术来实现。