公开(公告)号：US20110018059A1

公开(公告)日：2011-01-27

申请号：US12509379

申请日：2009-07-24

申请人： Dixie Dunn ,  Paul Thorup ,  Dean E. Probst ,  Michael D. Gruenhagen

发明人： Dixie Dunn ,  Paul Thorup ,  Dean E. Probst ,  Michael D. Gruenhagen

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/66143 ,  H01L29/66348 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7806 ,  H01L29/872 ,  H01L29/8725

摘要： A semiconductor structure comprises an active region comprising trenches extending into a semiconductor region. Each trench includes a shield electrode and a gate electrode. The semiconductor structure also comprises a shield contact region adjacent to the active region. The shield contact region comprises at least one contact trench extending into the semiconductor region. The shield electrode from at least one of the trenches in the active region extends along a length of the contact trench. The semiconductor structure also comprises an interconnect layer extending over the active region and the shield contact region. In the active region the interconnect layer is isolated from the gate electrode in each trench by a dielectric layer and contacts mesa surfaces of the semiconductor region adjacent to the trenches. In the shield contact region the interconnect layer contacts the shield electrode and the mesa surfaces of the semiconductor region adjacent to the contact trench.

摘要翻译： 半导体结构包括包括延伸到半导体区域中的沟槽的有源区。 每个沟槽包括屏蔽电极和栅电极。 半导体结构还包括与有源区相邻的屏蔽接触区。 屏蔽接触区域包括延伸到半导体区域中的至少一个接触沟槽。 有源区域中至少一个沟槽的屏蔽电极沿接触沟槽的长度延伸。 半导体结构还包括在有源区域和屏蔽接触区域上延伸的互连层。 在有源区域中，互连层通过介电层与每个沟槽中的栅电极隔离，并接触与沟槽相邻的半导体区域的台面表面。 在屏蔽接触区域中，互连层与屏蔽电极和与接触沟槽相邻的半导体区域的台面表面接触。

公开(公告)号：US20110275208A1

公开(公告)日：2011-11-10

申请号：US13104006

申请日：2011-05-09

申请人： Dixie Dunn ,  Paul Thorup ,  Dean E. Probst ,  Michael D. Gruenhagen

发明人： Dixie Dunn ,  Paul Thorup ,  Dean E. Probst ,  Michael D. Gruenhagen

IPC分类号： H01L21/28

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/66143 ,  H01L29/66348 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7806 ,  H01L29/872 ,  H01L29/8725

摘要： A semiconductor structure is formed as follows. Trenches are formed in a semiconductor region and a shield electrode is formed in each trench. Gate electrodes are formed in a portion of the trenches that form an active region. Each gate electrode is disposed over the shield electrode and is isolated from the shield electrode by an inter-electrode dielectric. An interconnect layer is formed extending over the trenches. The interconnect layer is isolated from the gate electrodes in the active region by a dielectric layer and contacts the shield electrodes in a shield contact region separate from the active region. The interconnect layer contacts mesa surfaces between adjacent trenches in the shield contact region.

摘要翻译： 如下形成半导体结构。 沟槽形成在半导体区域中，并且在每个沟槽中形成屏蔽电极。 栅电极形成在形成有源区的沟槽的一部分中。 每个栅电极设置在屏蔽电极之上，并且通过电极间电介质与屏蔽电极隔离。 形成在沟槽上延伸的互连层。 互连层通过介电层与有源区域中的栅电极隔离，并且在与有源区分离的屏蔽接触区域中与屏蔽电极接触。 互连层接触屏蔽接触区域中相邻沟槽之间的台面。

公开(公告)号：US08338285B2

公开(公告)日：2012-12-25

申请号：US13104006

申请日：2011-05-09

申请人： Dixie Dunn ,  Paul Thorup ,  Dean E. Probst ,  Michael D. Gruenhagen

发明人： Dixie Dunn ,  Paul Thorup ,  Dean E. Probst ,  Michael D. Gruenhagen

IPC分类号： H01L21/28

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/66143 ,  H01L29/66348 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7806 ,  H01L29/872 ,  H01L29/8725

摘要： A semiconductor structure is formed as follows. Trenches are formed in a semiconductor region and a shield electrode is formed in each trench. Gate electrodes are formed in a portion of the trenches that form an active region. Each gate electrode is disposed over the shield electrode and is isolated from the shield electrode by an inter-electrode dielectric. An interconnect layer is formed extending over the trenches. The interconnect layer is isolated from the gate electrodes in the active region by a dielectric layer and contacts the shield electrodes in a shield contact region separate from the active region. The interconnect layer contacts mesa surfaces between adjacent trenches in the shield contact region.

摘要翻译： 如下形成半导体结构。 沟槽形成在半导体区域中，并且在每个沟槽中形成屏蔽电极。 栅电极形成在形成有源区的沟槽的一部分中。 每个栅电极设置在屏蔽电极之上，并且通过电极间电介质与屏蔽电极隔离。 形成在沟槽上延伸的互连层。 互连层通过介电层与有源区域中的栅电极隔离，并且在与有源区分离的屏蔽接触区域中与屏蔽电极接触。 互连层接触屏蔽接触区域中相邻沟槽之间的台面。

公开(公告)号：US07952141B2

公开(公告)日：2011-05-31

申请号：US12509379

申请日：2009-07-24

申请人： Dixie Dunn ,  Paul Thorup ,  Dean E. Probst ,  Michael D. Gruenhagen

发明人： Dixie Dunn ,  Paul Thorup ,  Dean E. Probst ,  Michael D. Gruenhagen

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/66143 ,  H01L29/66348 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7806 ,  H01L29/872 ,  H01L29/8725

摘要： A semiconductor structure comprises an active region comprising trenches extending into a semiconductor region. Each trench includes a shield electrode and a gate electrode. The semiconductor structure also comprises a shield contact region adjacent to the active region. The shield contact region comprises at least one contact trench extending into the semiconductor region. The shield electrode from at least one of the trenches in the active region extends along a length of the contact trench. The semiconductor structure also comprises an interconnect layer extending over the active region and the shield contact region. In the active region the interconnect layer is isolated from the gate electrode in each trench by a dielectric layer and contacts mesa surfaces of the semiconductor region adjacent to the trenches. In the shield contact region the interconnect layer contacts the shield electrode and the mesa surfaces of the semiconductor region adjacent to the contact trench.

摘要翻译： 半导体结构包括包括延伸到半导体区域中的沟槽的有源区。 每个沟槽包括屏蔽电极和栅电极。 半导体结构还包括与有源区相邻的屏蔽接触区。 屏蔽接触区域包括延伸到半导体区域中的至少一个接触沟槽。 有源区域中至少一个沟槽的屏蔽电极沿接触沟槽的长度延伸。 半导体结构还包括在有源区域和屏蔽接触区域上延伸的互连层。 在有源区域中，互连层通过介电层与每个沟槽中的栅电极隔离，并接触与沟槽相邻的半导体区域的台面表面。 在屏蔽接触区域中，互连层与屏蔽电极和与接触沟槽相邻的半导体区域的台面表面接触。

公开(公告)号：US20110230046A1

公开(公告)日：2011-09-22

申请号：US13151495

申请日：2011-06-02

申请人： Michael D. Gruenhagen ,  Suku Kim ,  James J. Murphy ,  Eddy Tjhia ,  Chung-Lin Wu ,  Mark Larsen ,  Douglas E. Dolan

发明人： Michael D. Gruenhagen ,  Suku Kim ,  James J. Murphy ,  Eddy Tjhia ,  Chung-Lin Wu ,  Mark Larsen ,  Douglas E. Dolan

IPC分类号： H01L21/28

CPC分类号： H01L23/49513 ,  H01L23/49524 ,  H01L24/05 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L24/40 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/2518 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/73255 ,  H01L2224/73265 ,  H01L2224/83856 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/0105 ,  H01L2924/3512 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/37099

摘要： Disclosed are semiconductor dice with backside trenches filled with elastic conductive material. The trenches reduce the on-state resistances of the devices incorporated on the dice. The elastic conductive material provides a conductive path to the backsides of the die with little induced stress on the semiconductor die caused by thermal cycling. Also disclosed are packages using the dice, and methods of making the dice.

摘要翻译： 公开了具有填充有弹性导电材料的背面沟槽的半导体裸片。 沟槽减小了掺入骰子的器件的导通电阻。 弹性导电材料为模具的背面提供导电路径，在半导体芯片上由热循环引起的微小应力。 还公开了使用骰子的包裹以及制造骰子的方法。

公开(公告)号：US08058732B2

公开(公告)日：2011-11-15

申请号：US12275086

申请日：2008-11-20

申请人： Michael D. Gruenhagen ,  Suku Kim ,  James J. Murphy ,  Ihsiu Ho ,  Eddy Tjhia ,  Chung-Lin Wu ,  Mark Larsen ,  Rohit Dikshit

发明人： Michael D. Gruenhagen ,  Suku Kim ,  James J. Murphy ,  Ihsiu Ho ,  Eddy Tjhia ,  Chung-Lin Wu ,  Mark Larsen ,  Rohit Dikshit

IPC分类号： H01L23/48

CPC分类号： H01L29/7802 ,  H01L23/3114 ,  H01L23/36 ,  H01L23/482 ,  H01L24/16 ,  H01L24/19 ,  H01L24/31 ,  H01L29/0657 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/73253 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/351 ,  H01L2924/00

摘要： Disclosed are semiconductor die structures that enable a die having a vertical power device to be packaged in a wafer-level chip scale package where the current-conducting terminals are present at one surface of the die, and where the device has very low on-state resistance. In an exemplary embodiment, a trench and an aperture are formed in a backside of a die, with the aperture contacting a conductive region at the top surface of the die. A conductive layer and/or a conductive body may be disposed on the trench and aperture to electrically couple the backside current-conducting electrode of the device to the conductive region. Also disclosed are packages and systems using a die with a die structure according to the invention, and methods of making dice with a die structure according to the invention.

摘要翻译： 公开了半导体管芯结构，其使具有垂直功率器件的管芯封装在晶片级芯片级封装中，其中导电端子存在于管芯的一个表面处，并且器件具有非常低的导通状态 抵抗性。 在示例性实施例中，沟槽和孔形成在管芯的背面，孔与导管的顶表面处的导电区接触。 可以在沟槽和孔上设置导电层和/或导体，以将器件的背面导电电极电耦合到导电区域。 还公开了使用根据本发明的具有模具结构的模具的封装和系统，以及根据本发明的具有模具结构的模具的方法。

公开(公告)号：US20110062564A1

公开(公告)日：2011-03-17

申请号：US12561988

申请日：2009-09-17

申请人： Michael D. Gruenhagen ,  Rohit Dikshit

发明人： Michael D. Gruenhagen ,  Rohit Dikshit

IPC分类号： H01L23/495 ,  H01L21/50

CPC分类号： H01L29/0657 ,  H01L21/30608 ,  H01L21/78 ,  H01L23/49506 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Methods for singulating a semiconductor wafer into a plurality of individual dies that contain lateral edges or sidewalls and the semiconductor dies formed from these methods are described. The dies are formed from methods that use a front to back photolithography alignment process to form a photo-resist mask and an anisoptropic wet etch in an HNA and/or a TMAH solution on the backside of the wafer through the photoresist mask to form sloped sidewalls and/or textures. The conditions of the TMAH etching process can be controlled to form any desired combination of rough or smooth sidewalls. Thus, the dies formed have a Si front side with an area larger than the Si backside area and sidewalls or lateral edges that are not perpendicular to the front or back surface of the die. Other embodiments are also described.

摘要翻译： 描述了将半导体晶片分离成包含侧边缘或侧壁的多个单独晶粒以及由这些方法形成的半导体管芯的方法。 模具由使用从前到后的光刻对准工艺以通过光致抗蚀剂掩模在晶片背面上的HNA和/或TMAH溶液中形成光刻胶掩模和不对称湿蚀刻的方法形成，以形成倾斜的侧壁 和/或纹理。 可以控制TMAH蚀刻工艺的条件以形成粗糙或平滑侧壁的任何期望的组合。 因此，形成的模具具有比Si背面区域大的Si前侧和不垂直于模具的前表面或后表面的侧壁或侧边缘。 还描述了其它实施例。

公开(公告)号：US20090273082A1

公开(公告)日：2009-11-05

申请号：US12115254

申请日：2008-05-05

申请人： Suku Kim ,  James J. Murphy ,  Michael D. Gruenhagen ,  Matthew R. Reynolds ,  Romel N. Manatad ,  Jan Vincent Mancelita

发明人： Suku Kim ,  James J. Murphy ,  Michael D. Gruenhagen ,  Matthew R. Reynolds ,  Romel N. Manatad ,  Jan Vincent Mancelita

IPC分类号： H01L23/488 ,  H01L21/768

CPC分类号： H01L21/74 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00

摘要： Methods for localized thinning of wafers used in semiconductor devices and the structures formed from such methods are described. The methods thin localized areas of the backside of the semiconductor wafer to form recesses with a bi-directional channel design that is repeated within the wafer (or die) so that no straight channel line crosses the wafer (or die). The bi-directional pattern design keeps the channels from being aligned with the crystal orientation of the wafer. The recesses are then filled by a solder ball drop process by dropping proper size solder balls into the recesses and then annealing the wafer to reflow the solder balls and flatten them out. The reflow process begins to fill in the recesses from the bottom up, thereby avoiding void formation and the resulting air traps in the reflowed solder material. Other embodiments are also described.

摘要翻译： 描述了半导体器件中使用的晶片的局部变薄方法和由这些方法形成的结构。 该方法使半导体晶片的背面薄的局部区域形成具有在晶片（或管芯）内重复的双向通道设计的凹槽，使得没有直通道线穿过晶片（或管芯）。 双向图案设计保持通道不与晶片的晶体取向对齐。 然后通过将适当尺寸的焊球落入凹槽中然后通过焊球落下工艺填充凹陷，然后退火晶片以回流焊球并使其平坦化。 回流工艺开始从底部向上填充凹槽，从而避免了空隙形成和回流焊料中形成的空气阱。 还描述了其它实施例。

公开(公告)号：US08598035B2

公开(公告)日：2013-12-03

申请号：US13151495

申请日：2011-06-02

申请人： Michael D. Gruenhagen ,  Suku Kim ,  James J. Murphy ,  Eddy Tjhia ,  Chung-Lin Wu ,  Mark Larsen ,  Douglas E. Dolan

发明人： Michael D. Gruenhagen ,  Suku Kim ,  James J. Murphy ,  Eddy Tjhia ,  Chung-Lin Wu ,  Mark Larsen ,  Douglas E. Dolan

IPC分类号： H01L21/44

CPC分类号： H01L23/49513 ,  H01L23/49524 ,  H01L24/05 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L24/40 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/2518 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/73255 ,  H01L2224/73265 ,  H01L2224/83856 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/0105 ,  H01L2924/3512 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/37099

摘要： Disclosed are semiconductor dice with backside trenches filled with elastic conductive material. The trenches reduce the on-state resistances of the devices incorporated on the dice. The elastic conductive material provides a conductive path to the backsides of the die with little induced stress on the semiconductor die caused by thermal cycling. Also disclosed are packages using the dice, and methods of making the dice.

摘要翻译： 公开了具有填充有弹性导电材料的背面沟槽的半导体裸片。 沟槽减小了掺入骰子的器件的导通电阻。 弹性导电材料为模具的背面提供导电路径，在半导体芯片上由热循环引起的微小应力。 还公开了使用骰子的包裹以及制造骰子的方法。

公开(公告)号：US08502313B2

公开(公告)日：2013-08-06

申请号：US13091578

申请日：2011-04-21

申请人： Rohit Dikshit ,  Mark L. Rinehimer ,  Michael D. Gruenhagen ,  Joseph A. Yedinak ,  Tracie Petersen ,  Ritu Sodhi ,  Dan Kinzer ,  Christopher L. Rexer ,  Fred C. Session

发明人： Rohit Dikshit ,  Mark L. Rinehimer ,  Michael D. Gruenhagen ,  Joseph A. Yedinak ,  Tracie Petersen ,  Ritu Sodhi ,  Dan Kinzer ,  Christopher L. Rexer ,  Fred C. Session

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L24/05 ,  H01L29/41775 ,  H01L29/42372 ,  H01L29/7397 ,  H01L29/7455 ,  H01L29/7811 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2924/01327 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/01079 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/01023 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/00

摘要： This document discusses, among other things, a semiconductor device including a first metal layer coupled to a source region and a second metal layer coupled to a gate structure, wherein at least a portion of the first and second metal layers overlap vertically.

摘要翻译： 本文件尤其涉及包括耦合到源区的第一金属层和耦合到栅极结构的第二金属层的半导体器件，其中第一和第二金属层的至少一部分垂直重叠。