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公开(公告)号：US20100059857A1
公开(公告)日：2010-03-11
申请号：US12208862
申请日：2008-09-11
IPC分类号： H01L23/525 , H01L21/60 , H01L23/495
CPC分类号： H01L24/83 , C25D7/123 , H01L23/142 , H01L24/27 , H01L24/29 , H01L2224/83191 , H01L2224/83192 , H01L2224/83205 , H01L2224/83801 , H01L2224/8384 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01068 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/12044 , H01L2924/14 , H01L2924/1461 , H01L2924/157 , H01L2924/15747 , H01L2924/3512 , H01L2924/00 , H01L2924/00014
摘要： A method of fabricating a semiconductor device. One embodiment provides a metal carrier. A semiconductor chip is provided. A porous layer is produced at a surface of at least one of the carrier and the semiconductor chip. The semiconductor chip is placed on the carrier. The resulting structure is heated until the semiconductor chip is attached to the carrier.
摘要翻译： 一种制造半导体器件的方法。 一个实施例提供一种金属载体。 提供半导体芯片。 在载体和半导体芯片中的至少一个的表面上产生多孔层。 将半导体芯片放置在载体上。 将所得到的结构加热直到半导体芯片附着到载体上。
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公开(公告)号：US08603864B2
公开(公告)日：2013-12-10
申请号：US12208862
申请日：2008-09-11
IPC分类号： H01L21/00
CPC分类号： H01L24/83 , C25D7/123 , H01L23/142 , H01L24/27 , H01L24/29 , H01L2224/83191 , H01L2224/83192 , H01L2224/83205 , H01L2224/83801 , H01L2224/8384 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01068 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/12044 , H01L2924/14 , H01L2924/1461 , H01L2924/157 , H01L2924/15747 , H01L2924/3512 , H01L2924/00 , H01L2924/00014
摘要： A method of fabricating a semiconductor device. One embodiment provides a metal carrier. A semiconductor chip is provided. A porous layer is produced at a surface of at least one of the carrier and the semiconductor chip. The semiconductor chip is placed on the carrier. The resulting structure is heated until the semiconductor chip is attached to the carrier.
摘要翻译： 一种制造半导体器件的方法。 一个实施例提供一种金属载体。 提供半导体芯片。 在载体和半导体芯片中的至少一个的表面上产生多孔层。 将半导体芯片放置在载体上。 将所得到的结构加热直到半导体芯片附着到载体上。
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公开(公告)号：US20090108423A1
公开(公告)日：2009-04-30
申请号：US11924134
申请日：2007-10-25
IPC分类号： H01L23/495 , H01L21/02
CPC分类号： H01L23/3107 , H01L23/4334 , H01L23/49586 , H01L24/28 , H01L24/31 , H01L24/48 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2924/01004 , H01L2924/01068 , H01L2924/01078 , H01L2924/078 , H01L2924/12044 , H01L2924/1306 , H01L2924/14 , H01L2924/15747 , H01L2924/181 , H05K3/3426 , H05K2201/10689 , H05K2203/124 , Y02P70/613 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package includes a leadframe defining a die pad, a chip electrically coupled to the die pad, encapsulation material covering the chip and the die pad, and a plurality of lead ends exposed relative to the encapsulation material and configured for electrical communication with the chip, and a nitrogen-containing hydrocarbon coating disposed over at least the lead ends of the leadframe, where the hydrocarbon coating is free of metal particles.
摘要翻译： 半导体封装包括限定芯片焊盘的引线框架，电耦合到管芯焊盘的芯片，覆盖芯片和管芯焊盘的封装材料以及相对于封装材料暴露的多个引线端子，并被配置为与芯片电连通 ，以及设置在引线框架的至少引线端上的含氮烃涂层，其中烃涂层不含金属颗粒。
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4.发明申请METHOD OF MAKING AN INTEGRATED CIRCUIT INCLUDING ELECTRODEPOSITION OF ALUMINIUM 审中-公开制造包含铝电沉积的集成电路的方法公开(公告)号：US20080257744A1
公开(公告)日：2008-10-23
申请号：US11737530
申请日：2007-04-19
申请人： Johannes Lodermeyer , Edmund Riedl , Werner Robl
发明人： Johannes Lodermeyer , Edmund Riedl , Werner Robl
IPC分类号： C25D3/56
CPC分类号： C25D3/44 , C25D17/002 , C25D17/004 , C25D21/11
摘要： A method of making an integrated circuit including composition of matter for electrodepositing of aluminium is disclosed. One embodiment includes a bath having a solution of selected aluminium salts in a substantially anhydrous organic solvent, to uses of certain aluminium salts for electrodepositing and to processes for electrodepositing aluminium.
摘要翻译： 公开了一种制造集成电路的方法，该集成电路包括用于电沉积铝的物质的组成。 一个实施方案包括具有选定的铝盐在基本上无水的有机溶剂中的溶液的浴，使用某些铝盐进行电沉积和电沉积铝的方法。
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公开(公告)号：US07989930B2
公开(公告)日：2011-08-02
申请号：US11924134
申请日：2007-10-25
IPC分类号： H01L21/00
CPC分类号： H01L23/3107 , H01L23/4334 , H01L23/49586 , H01L24/28 , H01L24/31 , H01L24/48 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2924/01004 , H01L2924/01068 , H01L2924/01078 , H01L2924/078 , H01L2924/12044 , H01L2924/1306 , H01L2924/14 , H01L2924/15747 , H01L2924/181 , H05K3/3426 , H05K2201/10689 , H05K2203/124 , Y02P70/613 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package includes a leadframe defining a die pad, a chip electrically coupled to the die pad, encapsulation material covering the chip and the die pad, and a plurality of lead ends exposed relative to the encapsulation material and configured for electrical communication with the chip, and a nitrogen-containing hydrocarbon coating disposed over at least the lead ends of the leadframe, where the hydrocarbon coating is free of metal particles.
摘要翻译： 半导体封装包括限定芯片焊盘的引线框架，电耦合到管芯焊盘的芯片，覆盖芯片和管芯焊盘的封装材料以及相对于封装材料暴露的多个引线端子，并被配置为与芯片电连通 ，以及设置在引线框架的至少引线端上的含氮烃涂层，其中烃涂层不含金属颗粒。
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6.发明申请METHOD OF MAKING AN INTEGRATED CIRCUIT INCLUDING ELECTRODEPOSITION OF METALLIC CHROMIUM 有权制造包含金属铬电沉积的集成电路的方法公开(公告)号：US20080257743A1
公开(公告)日：2008-10-23
申请号：US11737536
申请日：2007-04-19
申请人： Johannes Lodermeyer , Edmund Riedl , Werner Robl
发明人： Johannes Lodermeyer , Edmund Riedl , Werner Robl
摘要： A method of making an integrated circuit including a composition of matter for electrodepositing of chromium is disclosed. One embodiment provides a bath having a solution of a chromium salt in a substantially anhydrous organic solvent, to uses of certain chromium salts for electrodepositing and to processes for electrodepositing chromium.
摘要翻译： 公开了一种制造集成电路的方法，该集成电路包括用于电沉积铬的物质组合物。 一个实施方案提供了一种具有铬盐在基本上无水的有机溶剂中的溶液的浴，用于某些铬盐的电沉积和电沉积铬的方法。
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7.发明授权Method of making an integrated circuit including electrodeposition of metallic chromium 有权制造包含电沉积金属铬的集成电路的方法公开(公告)号：US07909978B2
公开(公告)日：2011-03-22
申请号：US11737536
申请日：2007-04-19
申请人： Johannes Lodermeyer , Edmund Riedl , Werner Robl
发明人： Johannes Lodermeyer , Edmund Riedl , Werner Robl
摘要： A method of making an integrated circuit including a composition of matter for electrodepositing of chromium is disclosed. One embodiment provides a bath having a solution of a chromium salt in a substantially anhydrous organic solvent, to uses of certain chromium salts for electrodepositing and to processes for electrodepositing chromium.
摘要翻译： 公开了一种制造集成电路的方法，该集成电路包括用于电沉积铬的物质组合物。 一个实施方案提供了一种具有铬盐在基本上无水的有机溶剂中的溶液的浴，用于某些铬盐的电沉积和电沉积铬的方法。
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8.发明授权公开(公告)号：US08975711B2
公开(公告)日：2015-03-10
申请号：US13314438
申请日：2011-12-08
IPC分类号： H01L29/72 , H01L23/00 , H01L23/492 , H01L21/48 , H01L23/538 , H01L21/56 , H01L25/07 , H01L25/00 , H01L23/31
CPC分类号： H01L25/50 , H01L21/4857 , H01L21/568 , H01L21/76897 , H01L23/3107 , H01L23/492 , H01L23/5389 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/14 , H01L24/24 , H01L24/73 , H01L24/82 , H01L24/96 , H01L25/071 , H01L25/072 , H01L2224/02379 , H01L2224/02381 , H01L2224/0401 , H01L2224/04105 , H01L2224/05548 , H01L2224/05567 , H01L2224/05624 , H01L2224/05647 , H01L2224/1132 , H01L2224/11849 , H01L2224/12105 , H01L2224/131 , H01L2224/1411 , H01L2224/14181 , H01L2224/16225 , H01L2224/16227 , H01L2224/16245 , H01L2224/24011 , H01L2224/2402 , H01L2224/24105 , H01L2224/24135 , H01L2224/245 , H01L2224/40105 , H01L2224/40227 , H01L2224/73209 , H01L2224/73267 , H01L2224/82106 , H01L2224/96 , H01L2924/00014 , H01L2924/01322 , H01L2924/12042 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13062 , H01L2924/13091 , H01L2924/1461 , H01L2924/181 , H01L2224/03 , H01L2224/11 , H01L2224/81 , H01L2224/84 , H01L2924/00012 , H01L2924/01029 , H01L2924/00 , H01L2924/014 , H01L2224/05552
摘要： A device includes a first power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The device further includes a second power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The first and second power semiconductor chips are arranged one above another, and the first face of the first power semiconductor chip faces in the direction of the first face of the second power semiconductor chip. In addition, the first power semiconductor chip is located laterally at least partially outside of the outline of the second power semiconductor chip.
摘要翻译： 一种器件包括具有第一接触焊盘的第一功率半导体芯片和第一面上的第二接触焊盘以及第二面上的第三接触焊盘。 该器件还包括具有第一接触焊盘的第二功率半导体芯片和第一面上的第二接触焊盘以及第二面上的第三接触焊盘。 第一功率半导体芯片和第二功率半导体芯片彼此重叠配置，第一功率半导体芯片的第一面朝向第二功率半导体芯片的第一面的方向。 此外，第一功率半导体芯片至少部分地位于第二功率半导体芯片的轮廓外侧。
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公开(公告)号：US20130146991A1
公开(公告)日：2013-06-13
申请号：US13314438
申请日：2011-12-08
IPC分类号： H01L25/07 , H01L21/60 , H01L23/538
CPC分类号： H01L25/50 , H01L21/4857 , H01L21/568 , H01L21/76897 , H01L23/3107 , H01L23/492 , H01L23/5389 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/14 , H01L24/24 , H01L24/73 , H01L24/82 , H01L24/96 , H01L25/071 , H01L25/072 , H01L2224/02379 , H01L2224/02381 , H01L2224/0401 , H01L2224/04105 , H01L2224/05548 , H01L2224/05567 , H01L2224/05624 , H01L2224/05647 , H01L2224/1132 , H01L2224/11849 , H01L2224/12105 , H01L2224/131 , H01L2224/1411 , H01L2224/14181 , H01L2224/16225 , H01L2224/16227 , H01L2224/16245 , H01L2224/24011 , H01L2224/2402 , H01L2224/24105 , H01L2224/24135 , H01L2224/245 , H01L2224/40105 , H01L2224/40227 , H01L2224/73209 , H01L2224/73267 , H01L2224/82106 , H01L2224/96 , H01L2924/00014 , H01L2924/01322 , H01L2924/12042 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13062 , H01L2924/13091 , H01L2924/1461 , H01L2924/181 , H01L2224/03 , H01L2224/11 , H01L2224/81 , H01L2224/84 , H01L2924/00012 , H01L2924/01029 , H01L2924/00 , H01L2924/014 , H01L2224/05552
摘要： A device includes a first power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The device further includes a second power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The first and second power semiconductor chips are arranged one above another, and the first face of the first power semiconductor chip faces in the direction of the first face of the second power semiconductor chip. In addition, the first power semiconductor chip is located laterally at least partially outside of the outline of the second power semiconductor chip.
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