公开(公告)号：US5631499A

公开(公告)日：1997-05-20

申请号：US656902

申请日：1996-06-03

申请人： Eiichi Hosomi ,  Chiaki Takubo ,  Hiroshi Tazawa ,  Ryouichi Miyamoto ,  Takashi Arai ,  Koji Shibasaki

发明人： Eiichi Hosomi ,  Chiaki Takubo ,  Hiroshi Tazawa ,  Ryouichi Miyamoto ,  Takashi Arai ,  Koji Shibasaki

IPC分类号： H01L21/28 ,  H01L21/321 ,  H01L21/60 ,  H01L23/485 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05562 ,  H01L2224/05572 ,  H01L2224/11 ,  H01L2224/1147 ,  H01L2224/13 ,  H01L2224/13006 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01072 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/14

摘要： A semiconductor device having a bump electrode includes a first conductive layer formed on a predetermined portion of a substrate. An insulating layer is formed on the substrate and the first conductive layer. The insulating layer has an opening portion such that a predetermined portion of the first conductive layer is exposed. A second conductive layer is formed on the first conductive layer, a side wall of the opening portion of the insulating layer, and an upper surface of the insulating layer. A third conductive layer is formed to cover at least the insulating layer on the first conductive layer and the second conductive layer along the portion. A fourth conductive layer is formed on the third conductive layer to have an over hang portion. A side etch portion is formed surrounded with an over hang portion of the fourth conductive layer, the third conductive layer, and the insulating layer.

摘要翻译： 具有凸块电极的半导体器件包括形成在基板的预定部分上的第一导电层。 在基板和第一导电层上形成绝缘层。 绝缘层具有使得第一导电层的预定部分露出的开口部。 在第一导电层，绝缘层的开口部分的侧壁和绝缘层的上表面上形成第二导电层。 形成第三导电层以至少覆盖沿着该部分的第一导电层和第二导电层上的绝缘层。 在第三导电层上形成第四导电层以具有过悬挂部分。 侧蚀刻部分形成为由第四导电层，第三导电层和绝缘层的悬垂部分围绕。

公开(公告)号：US6061466A

公开(公告)日：2000-05-09

申请号：US773054

申请日：1996-12-24

申请人： Chiaki Takubo ,  Eiichi Hosomi ,  Hiroshi Tazawa ,  Koji Shibasaki

发明人： Chiaki Takubo ,  Eiichi Hosomi ,  Hiroshi Tazawa ,  Koji Shibasaki

IPC分类号： G01B11/02 ,  G01N21/88 ,  G01R31/04 ,  G01R31/309 ,  G06T7/00 ,  H01L21/60 ,  H01L21/66 ,  G06K9/00

CPC分类号： G06T7/0004 ,  G01N21/88 ,  G01R31/046 ,  G01R31/309 ,  G06T2207/30148

摘要： Disclosed is an apparatus and method for inspecting a connection state of a lead electrode to a bump after TAB (tape automated bonding). An LSI chip is immobilized on a stage. A flexible lead is held by a holding portion and connected to a bump. Above the chip, a CCD camera is provided. The stage is controlled to move up and down by a moving control mechanism. Each of the lead/bump connection states immediately after ILB (Inner lead bonding) is taken in the form of image data and defined as a first image data. A second image data of the lead/bump connection state is taken after the bump and lead are moved to different positions by moving the stage in order to change the position of the chip by means of the moving control mechanism. Whether or not the lead is duly connected to the bump is determined by the comparison of the first and second image data.

摘要翻译： 公开了一种用于在TAB（带自动接合）之后检查引线电极与凸块的连接状态的装置和方法。 将LSI芯片固定在台上。 柔性引线由保持部分保持并连接到凸块。 在芯片之上，提供了一个CCD相机。 通过移动控制机构控制舞台上下移动。 在ILB（内引线接合）之后紧接着的引导/碰撞连接状态以图像数据的形式获取并被定义为第一图像数据。 引导/凸起连接状态的第二图像数据是在通过移动台之后将凸起和引线移动到不同位置之后进行的，以通过移动控制机构改变芯片的位置。 通过第一和第二图像数据的比较来确定引线是否正确连接到凸块。

公开(公告)号：US6111317A

公开(公告)日：2000-08-29

申请号：US784814

申请日：1997-01-16

申请人： Takashi Okada ,  Naohiko Hirano ,  Hiroshi Tazawa ,  Eiichi Hosomi ,  Chiaki Takubo ,  Kazuhide Doi ,  Yoichi Hiruta ,  Koji Shibasaki

发明人： Takashi Okada ,  Naohiko Hirano ,  Hiroshi Tazawa ,  Eiichi Hosomi ,  Chiaki Takubo ,  Kazuhide Doi ,  Yoichi Hiruta ,  Koji Shibasaki

IPC分类号： H01L23/485 ,  H01L23/528 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14

摘要： A first insulating film is formed on an integrated circuit chip on which an I/O pad is formed. A first opening portion is formed above the I/O pad. A conductive layer and a barrier metal layer which are electrically connected to the I/O pad through the first opening portion are stacked on the first insulating film. The conductive layer and the barrier metal layer are patterned by a single mask. A second insulating film is formed on the resultant structure. A second opening portion is formed in the second insulating film at a position different from that of the first opening portion. A solder bump or metal pad is formed on the barrier metal layer in the second opening portion. The position of the solder bump or metal pad is defined by the second opening portion.

摘要翻译： 在其上形成有I / O焊盘的集成电路芯片上形成第一绝缘膜。 第一开口部分形成在I / O焊盘上方。 通过第一开口部分电连接到I / O焊盘的导电层和阻挡金属层堆叠在第一绝缘膜上。 导电层和阻挡金属层通过单个掩模图案化。 在所得结构上形成第二绝缘膜。 在第二绝缘膜上形成与第一开口部不同的位置的第二开口部。 在第二开口部分的阻挡金属层上形成焊料凸块或金属焊盘。 焊料凸块或金属焊盘的位置由第二开口部分限定。

公开(公告)号：US5747881A

公开(公告)日：1998-05-05

申请号：US593622

申请日：1996-01-30

申请人： Eiichi Hosomi ,  Hiroshi Tazawa ,  Chiaki Takubo ,  Koji Shibasaki

发明人： Eiichi Hosomi ,  Hiroshi Tazawa ,  Chiaki Takubo ,  Koji Shibasaki

IPC分类号： H01L21/60 ,  H01L21/603 ,  H01L23/495 ,  H01L23/50 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/49572 ,  H01L23/49582 ,  H01L2224/05027 ,  H01L2224/05572 ,  H01L2924/0002 ,  H01L2924/01322

摘要： A semiconductor device comprises a semiconductor chip, an Au bump formed on the semiconductor chip, and Cu lead bonded to the Au bump through a bonding part. The Cu lead has a Cu core and a plated Sn layer formed on the Cu core, and the bonding part is formed of an Au--rich Au--Cu--Sn alloy of a ternary system having a single-phase structure with a composition of 15 atomic % Sn or less and 25 atomic % Cu or less.

摘要翻译： 半导体器件包括半导体芯片，形成在半导体芯片上的Au凸块，以及通过接合部分接合到Au凸块的Cu引线。 Cu引线具有在Cu芯上形成的Cu芯和镀Sn Sn，并且接合部由具有组成为15的单相结构的三元体系的富Au Au-Cu-Sn合金形成 原子％Sn以下且25原子％以下的Cu以下。

公开(公告)号：US6049130A

公开(公告)日：2000-04-11

申请号：US853475

申请日：1997-05-09

申请人： Eiichi Hosomi ,  Hiroshi Tazawa ,  Chiaki Takubo ,  Koji Shibasaki

发明人： Eiichi Hosomi ,  Hiroshi Tazawa ,  Chiaki Takubo ,  Koji Shibasaki

IPC分类号： H01L21/60 ,  H01L21/603 ,  H01L23/495 ,  H01L23/50 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L23/49572 ,  H01L23/49582 ,  H01L2224/05027 ,  H01L2224/05572 ,  H01L2924/0002 ,  H01L2924/01322

摘要： A semiconductor device comprises a semiconductor chip, an Au bump formed on the semiconductor chip, and Cu lead bonded to the Au bump through a bonding part. The Cu lead has a Cu core and a plated Sn layer formed on the Cu core, and the bonding part is formed of an Au-rich Au--Cu--Sn alloy of a ternary system having a single-phase structure containing 15 at. % or less Sn and 25 at. % or less Cu.

摘要翻译： 半导体器件包括半导体芯片，形成在半导体芯片上的Au凸块，以及通过接合部分接合到Au凸块的Cu引线。 Cu引线具有形成在Cu芯上的Cu芯和镀Sn Sn，并且所述接合部由具有包含15at的单相结构的三元体系的富Au Au-Cu-Sn合金形成。 ％以下Sn和25 at。 ％以下Cu。

公开(公告)号：US5825081A

公开(公告)日：1998-10-20

申请号：US729420

申请日：1996-10-11

申请人： Eiichi Hosomi ,  Chiaki Takubo ,  Hiroshi Tazawa ,  Koji Shibasaki

发明人： Eiichi Hosomi ,  Chiaki Takubo ,  Hiroshi Tazawa ,  Koji Shibasaki

IPC分类号： H01L21/60 ,  H01L23/495

CPC分类号： H01L23/49572 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253

摘要： The present invention is characterized by providing leads not contributing to actual connection outside the corner leads to prevent the deformation of the corner leads and improve the yield of tape carriers. A device hole is made in a near-central place of an insulating resin film. Around the device hole, outer-lead holes are made. On the insulating resin film, a plurality of wiring patterns are provided and forced to project into the device hole. The plurality of wiring patterns are formed into a plurality of inner leads, of which the outermost ones are determined to be corner leads. On each corner of the device hole, an aligning mark is provided. Dummy leads are provided closer to the aligning marks. The dummy leads are made shorter than the inner leads and corner leads.

摘要翻译： 本发明的特征在于，提供不会在拐角引线外部实际连接的引线，以防止拐角引线的变形并提高带状载体的产量。 在绝缘树脂膜的近中心位置制造器件孔。 围绕设备孔，制成外引线孔。 在绝缘树脂膜上，设置多个布线图案并强制突出到装置孔中。 多个布线图案形成为多个内引线，其中最外侧的引线被确定为拐角引线。 在设备孔的每个角上，提供对准标记。 靠近对准标记提供虚拟引线。 虚拟引线比内引线和角引脚短。

公开(公告)号：US5801447A

公开(公告)日：1998-09-01

申请号：US637242

申请日：1996-04-24

申请人： Naohiko Hirano ,  Kazuhide Doi ,  Chiaki Takubo ,  Hiroshi Tazawa ,  Eiichi Hosomi ,  Yoichi Hiruta ,  Takashi Okada ,  Koji Shibasaki

发明人： Naohiko Hirano ,  Kazuhide Doi ,  Chiaki Takubo ,  Hiroshi Tazawa ,  Eiichi Hosomi ,  Yoichi Hiruta ,  Takashi Okada ,  Koji Shibasaki

IPC分类号： H01L21/60 ,  H01L21/56 ,  H01L23/28 ,  H01L23/498 ,  H01L23/48

CPC分类号： H01L23/49838 ,  H01L21/563 ,  H01L24/29 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/14177 ,  H01L2224/16225 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15787 ,  H01L2924/351

摘要： In a flip chip mounting type semiconductor device, on a corner portion of a chip subjected to flip chip mounting, a gate region for injecting a sealing member filled between a mounted board and the chip is arranged. In this semiconductor device, a semiconductor element has a plurality of bumps formed on the peripheral portion on a major surface along each side, a plurality of pad electrodes are formed on the major surface of the circuit board, and the pad electrodes join the bumps. A resin sealing member is filled between the semiconductor element and the circuit board. A gate region through which the resin sealing member is injected is formed on a corner portion of the semiconductor element. In the gate region, no bump is formed, or bumps are arranged at intervals smaller than that in another region. For this reason, the resin uniformly enters the space between the semiconductor element and the circuit board through the gate region.

摘要翻译： 在倒装芯片安装型半导体器件中，在经过倒装芯片安装的芯片的角部上布置有用于注入填充在安装板和芯片之间的密封构件的栅极区域。 在该半导体装置中，半导体元件具有形成在沿着各侧的主表面的周边部分上的多个凸块，在电路板的主表面上形成有多个焊盘电极，并且焊盘电极与凸点接合。 在半导体元件和电路板之间填充树脂密封构件。 在半导体元件的角部形成有注入树脂密封构件的栅极区域。 在栅极区域中，没有形成凸起，或者凸块以比另一个区域小的间隔排列。 因此，树脂通过栅极区域均匀地进入半导体元件与电路基板之间的空间。

公开(公告)号：US5773888A

公开(公告)日：1998-06-30

申请号：US555392

申请日：1995-11-09

申请人： Eiichi Hosomi ,  Chiaki Takubo ,  Hiroshi Tazawa ,  Koji Shibasaki

发明人： Eiichi Hosomi ,  Chiaki Takubo ,  Hiroshi Tazawa ,  Koji Shibasaki

IPC分类号： H01L21/60 ,  H01L23/485 ,  H01L29/41

CPC分类号： H01L24/13 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13027 ,  H01L2224/13099 ,  H01L2224/14104 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/181

摘要： A semiconductor device having bump electrodes, each having a structure wherein an alloy layer such as Au--Sn formed by the reaction between the Sn-plated layer on the surface of the inner lead and the bump electrode never reach the bottom surface of the passivation opening portion, is provided. The center of the passivation opening portion is displaced apart from the center of an electrode pad to a direction toward the center of the semiconductor substrate. The center of the passivation opening portion is displaced away from the outer lead and close to the tip end of the inner lead in contrast to the center of the bump electrode. By positioning the passivation opening portion such that the center thereof is located nearer to the center of semiconductor substrate than a center of the bump electrode, without changing the height of the bump electrode or the size of the passivation opening portion, the Au--Sn alloy etc. caused by the reaction between the Sn-plated layer of the inner lead and the metal layer of the bump electrode can be prevented from reaching the passivation opening portion.

摘要翻译： 具有凸起电极的半导体器件，每个具有这样的结构，其中通过内引线表面上的Sn镀层与凸块电极之间的反应形成的诸如Au-Sn的合金层不会到达钝化开口的底表面 部分。 钝化开口部分的中心从电极焊盘的中心偏离朝向半导体衬底的中心的方向。 与凸起电极的中心相比，钝化开口部分的中心远离外部引线移动并且靠近内部引线的尖端。 通过将钝化开口部分定位成使得其中心位于比突起电极的中心更靠近半导体衬底的中心的位置，而不改变突起电极的高度或钝化开口部分的尺寸，Au-Sn合金 可以防止由内引线的镀Sn层与凸起电极的金属层之间的反应引起的等等到达钝化开口部分。

公开(公告)号：US5615822A

公开(公告)日：1997-04-01

申请号：US532281

申请日：1995-09-22

申请人： Chiaki Takubo ,  Hiroshi Tazawa ,  Eiichi Hosomi ,  Koji Shibasaki

发明人： Chiaki Takubo ,  Hiroshi Tazawa ,  Eiichi Hosomi ,  Koji Shibasaki

IPC分类号： B23K1/00 ,  H01L21/60 ,  H01L21/603

CPC分类号： H01L24/86 ,  B23K1/0016 ,  B23K2201/36 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01082 ,  H01L2924/12042

摘要： In this invention, a designed value of a lead width is previously input and a bonding load suitable for the designed lead width is previously input before the step of continuously bonding a TAB tape on a semiconductor chip is effected. Next, the TAB tape and chip are carried to preset positions, and after recognition of the positions of the tape and chip and the alignment of the tape and chip by use of a CCD camera are completed, the inner lead width is actually measured by use of the CCD camera. The measured lead width is compared with the designed lead width, and when a difference therebetween exceeds a preset reference value, the bonding load is changed to a bonding load suitable for the measured lead width of the lead to be actually bonded based on the ratio of the measured lead width to the designed lead width and then the bonding operation is effected by the suitable bonding load.

摘要翻译： 在本发明中，预先输入引线宽度的设计值，并且在进行连续接合半导体芯片上的TAB带的步骤之前，预先输入适合于设计的引线宽度的接合负载。 接下来，TAB带和芯片被携带到预设位置，并且在识别到带和芯片的位置以及通过使用CCD照相机的带和芯片的对准完成之后，实际上通过使用测量内引线宽度 的CCD相机。 将测量的引线宽度与设计的引线宽度进行比较，并且当它们之间的差异超过预设的参考值时，将接合负载改变为适合实际接合的引线的测量引线宽度的接合负载， 测量的引线宽度与设计的引线宽度，然后结合操作由适当的焊接负载来实现。

公开(公告)号：US06376907B1

公开(公告)日：2002-04-23

申请号：US09201866

申请日：1998-11-30

申请人： Eiji Takano ,  Eiichi Hosomi ,  Chiaki Takubo

发明人： Eiji Takano ,  Eiichi Hosomi ,  Chiaki Takubo

IPC分类号： H01L2312

CPC分类号： H01L23/04 ,  H01L23/10 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/16151 ,  H01L2924/16152 ,  H01L2924/16251 ,  H01L2224/0401

摘要： A semiconductor device with a BGA package includes a substrate made of a resin and having one side on which a number of solder ball terminals are formed and the other side on which a chip mounting portion electrically connected to the solder ball terminals is formed, and a cover plate made of a metal and attached to a semiconductor chip so as to cover and come into contact with it under a condition where the semiconductor chip is connected to the resin substrate by a flip-chip process. The cover plate includes a base brought into contact with the semiconductor chip and a peripheral portion formed with a plurality of bonding portions where the cover plate is bonded to the substrate. The bonding portions are discontinuous to each other.

摘要翻译： 具有BGA封装的半导体器件包括由树脂制成的衬底，其一侧形成有多个焊球端子，另一侧形成有与焊球端子电连接的芯片安装部， 由金属构成的盖板，并且在半导体芯片通过倒装芯片工艺连接到树脂基板的状态下被覆盖并与其接触。 盖板包括与半导体芯片接触的基座和形成有多个接合部分的边缘部分，其中盖板结合到基板。 接合部彼此不连续。