公开(公告)号：US5801447A

公开(公告)日：1998-09-01

申请号：US637242

申请日：1996-04-24

申请人： Naohiko Hirano ,  Kazuhide Doi ,  Chiaki Takubo ,  Hiroshi Tazawa ,  Eiichi Hosomi ,  Yoichi Hiruta ,  Takashi Okada ,  Koji Shibasaki

发明人： Naohiko Hirano ,  Kazuhide Doi ,  Chiaki Takubo ,  Hiroshi Tazawa ,  Eiichi Hosomi ,  Yoichi Hiruta ,  Takashi Okada ,  Koji Shibasaki

IPC分类号： H01L21/60 ,  H01L21/56 ,  H01L23/28 ,  H01L23/498 ,  H01L23/48

CPC分类号： H01L23/49838 ,  H01L21/563 ,  H01L24/29 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/14177 ,  H01L2224/16225 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15787 ,  H01L2924/351

摘要： In a flip chip mounting type semiconductor device, on a corner portion of a chip subjected to flip chip mounting, a gate region for injecting a sealing member filled between a mounted board and the chip is arranged. In this semiconductor device, a semiconductor element has a plurality of bumps formed on the peripheral portion on a major surface along each side, a plurality of pad electrodes are formed on the major surface of the circuit board, and the pad electrodes join the bumps. A resin sealing member is filled between the semiconductor element and the circuit board. A gate region through which the resin sealing member is injected is formed on a corner portion of the semiconductor element. In the gate region, no bump is formed, or bumps are arranged at intervals smaller than that in another region. For this reason, the resin uniformly enters the space between the semiconductor element and the circuit board through the gate region.

摘要翻译： 在倒装芯片安装型半导体器件中，在经过倒装芯片安装的芯片的角部上布置有用于注入填充在安装板和芯片之间的密封构件的栅极区域。 在该半导体装置中，半导体元件具有形成在沿着各侧的主表面的周边部分上的多个凸块，在电路板的主表面上形成有多个焊盘电极，并且焊盘电极与凸点接合。 在半导体元件和电路板之间填充树脂密封构件。 在半导体元件的角部形成有注入树脂密封构件的栅极区域。 在栅极区域中，没有形成凸起，或者凸块以比另一个区域小的间隔排列。 因此，树脂通过栅极区域均匀地进入半导体元件与电路基板之间的空间。

公开(公告)号：US6111317A

公开(公告)日：2000-08-29

申请号：US784814

申请日：1997-01-16

申请人： Takashi Okada ,  Naohiko Hirano ,  Hiroshi Tazawa ,  Eiichi Hosomi ,  Chiaki Takubo ,  Kazuhide Doi ,  Yoichi Hiruta ,  Koji Shibasaki

发明人： Takashi Okada ,  Naohiko Hirano ,  Hiroshi Tazawa ,  Eiichi Hosomi ,  Chiaki Takubo ,  Kazuhide Doi ,  Yoichi Hiruta ,  Koji Shibasaki

IPC分类号： H01L23/485 ,  H01L23/528 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14

摘要： A first insulating film is formed on an integrated circuit chip on which an I/O pad is formed. A first opening portion is formed above the I/O pad. A conductive layer and a barrier metal layer which are electrically connected to the I/O pad through the first opening portion are stacked on the first insulating film. The conductive layer and the barrier metal layer are patterned by a single mask. A second insulating film is formed on the resultant structure. A second opening portion is formed in the second insulating film at a position different from that of the first opening portion. A solder bump or metal pad is formed on the barrier metal layer in the second opening portion. The position of the solder bump or metal pad is defined by the second opening portion.

摘要翻译： 在其上形成有I / O焊盘的集成电路芯片上形成第一绝缘膜。 第一开口部分形成在I / O焊盘上方。 通过第一开口部分电连接到I / O焊盘的导电层和阻挡金属层堆叠在第一绝缘膜上。 导电层和阻挡金属层通过单个掩模图案化。 在所得结构上形成第二绝缘膜。 在第二绝缘膜上形成与第一开口部不同的位置的第二开口部。 在第二开口部分的阻挡金属层上形成焊料凸块或金属焊盘。 焊料凸块或金属焊盘的位置由第二开口部分限定。

公开(公告)号：US5648686A

公开(公告)日：1997-07-15

申请号：US506930

申请日：1995-07-26

申请人： Naohiko Hirano ,  Kazuhide Doi ,  Masayuki Miura ,  Takashi Okada ,  Yoichi Hiruta

发明人： Naohiko Hirano ,  Kazuhide Doi ,  Masayuki Miura ,  Takashi Okada ,  Yoichi Hiruta

IPC分类号： H01L21/60 ,  H01L23/485 ,  H01L23/48

CPC分类号： H01L24/10 ,  H01L24/13 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  Y10S257/915

摘要： An Al layer which serves as a lead-out electrode is formed on a semiconductor chip. An insulating layer is formed on the semiconductor chip and the Al layer. The insulating layer has an opening formed in that portion thereof which is located on the Al layer, thereby exposing a portion of the Al layer. A multi-level metal layer (barrier metal layer) is formed on the exposed portion of the Al layer and on that portion of the insulating layer which is located along the edge of the opening. A metallic nitride region is provided between a first-level metal layer in the multi-level metal layer and the insulating layer so as to be selectively formed at or under a peripheral portion of the first-level metal layer. A bump electrode is provided on the multi-level metal layer. The resultant semiconductor device is mounted on a circuit board by flip chip bonding, with the bump electrode interposed therebetween.

摘要翻译： 在半导体芯片上形成用作引出电极的Al层。 在半导体芯片和Al层上形成绝缘层。 绝缘层在其部分形成有开口，该开口位于Al层上，从而露出Al层的一部分。 在Al层的露出部分和位于开口边缘的绝缘层的那部分上形成多层金属层（阻挡金属层）。 金属氮化物区域设置在多层金属层中的第一级金属层与绝缘层之间，以便选择性地形成在第一级金属层的周边部分或下方。 在多层金属层上设置凸块电极。 所得到的半导体器件通过倒装芯片接合安装在电路板上，凸起电极插在其间。

公开(公告)号：US5629566A

公开(公告)日：1997-05-13

申请号：US512165

申请日：1995-08-07

申请人： Kazuhide Doi ,  Masayuki Miura ,  Takashi Okada ,  Naohiko Hirano ,  Yoichi Hiruta

发明人： Kazuhide Doi ,  Masayuki Miura ,  Takashi Okada ,  Naohiko Hirano ,  Yoichi Hiruta

IPC分类号： H01L23/28 ,  H01L21/56 ,  H01L21/60 ,  H01L23/02 ,  H01L23/04 ,  H01L23/10 ,  H01L23/13 ,  H01L23/29 ,  H01L23/31 ,  H01L23/12 ,  H01L23/48

CPC分类号： H01L24/31 ,  H01L21/563 ,  H01L23/13 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/06102 ,  H01L2224/13111 ,  H01L2224/16238 ,  H01L2224/26175 ,  H01L2224/29076 ,  H01L2224/29111 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83104 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83951 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15787 ,  H01L2924/351

摘要： A semiconductor device includes a semiconductor chip which is connected to a circuit substrate via solder bumps by flip-chip connection, a first encapsulant having a large Young's modulus and filling a space between the semiconductor chip and the circuit substrate in the central portion of the semiconductor chip, and a second encapsulant having a small Young's modulus and filling a space between the semiconductor chip and the circuit substrate in the peripheral portion of the semiconductor chip. A method for manufacturing the semiconductor device includes flowing the second encapsulant into position, but not the first encapsulant.

摘要翻译： 半导体器件包括通过倒装芯片连接通过焊料凸块连接到电路基板的半导体芯片，具有大的杨氏模量的第一密封剂，并且在半导体的中心部分填充半导体芯片和电路基板之间的空间 芯片和具有小杨氏模量的第二密封剂，并且在半导体芯片的周边部分填充半导体芯片和电路基板之间的空间。 一种用于制造半导体器件的方法包括使第二密封剂流入就位，而不是第一密封剂。

公开(公告)号：US5401688A

公开(公告)日：1995-03-28

申请号：US118786

申请日：1993-09-09

申请人： Yasuhiro Yamaji ,  Yoichi Hiruta ,  Tsutomu Nakazawa ,  Katsuto Katoh ,  Yoshihiro Atsumi ,  Naohiko Hirano ,  Akihiro Mase

发明人： Yasuhiro Yamaji ,  Yoichi Hiruta ,  Tsutomu Nakazawa ,  Katsuto Katoh ,  Yoshihiro Atsumi ,  Naohiko Hirano ,  Akihiro Mase

IPC分类号： H01L21/60 ,  H01L23/12 ,  H01L23/31 ,  H01L23/522 ,  H01L23/538 ,  H01L25/065 ,  H05K1/18

CPC分类号： H01L24/18 ,  H01L23/3164 ,  H01L23/5387 ,  H01L24/82 ,  H01L25/0655 ,  H05K1/186 ,  H01L2224/16225 ,  H01L2224/18 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K2201/091 ,  H05K2201/10674 ,  H05K3/4614 ,  H05K3/4632 ,  Y10T156/1002 ,  Y10T29/4913

摘要： A semiconductor chip is packaged within film carriers which serve as the enclosure of the semiconductor chip. The finished semiconductor device is flexible, bendable, and very thin. In manufacturing this semiconductor device, the process of laminating film carriers, the process of electrically connecting the semiconductor chip and film carriers, and the process of sealing the semiconductor chip, can be performed at the same time, shortening the manufacturing time and reducing manufacturing cost.

摘要翻译： 将半导体芯片封装在用作半导体芯片外壳的薄膜载体内。 成品半导体器件灵活，可弯曲，非常薄。 在制造该半导体器件时，可以同时进行层压薄膜载体的工艺，电连接半导体芯片和薄膜载体的工艺以及密封半导体芯片的工艺，缩短制造时间并降低制造成本 。

公开(公告)号：US5645123A

公开(公告)日：1997-07-08

申请号：US352780

申请日：1994-12-01

申请人： Kazuhide Doi ,  Naohiko Hirano

发明人： Kazuhide Doi ,  Naohiko Hirano

IPC分类号： H01L21/60 ,  H01L23/34 ,  H01L23/58 ,  H05K1/02 ,  H05K3/34 ,  F25B29/00

CPC分类号： H01L23/34 ,  H01L23/345 ,  H01L2224/16225 ,  H01L2924/10253 ,  H05K1/0201 ,  H05K3/3431

摘要： A semiconductor device according to the present invention includes a resistant heating element as a temperature regulation means on a circuit board. A semiconductor chip of the device is connected to the circuit board through connecting electrodes. A difference in temperature between the semiconductor chip and circuit board is kept at a fixed value by controlling the resistant heating element.

摘要翻译： 根据本发明的半导体器件包括作为电路板上的温度调节装置的耐电加热元件。 器件的半导体芯片通过连接电极连接到电路板。 通过控制耐电加热元件，将半导体芯片和电路板之间的温度差保持在固定值。

公开(公告)号：US5530289A

公开(公告)日：1996-06-25

申请号：US286165

申请日：1994-08-05

申请人： Naohiko Hirano ,  Kazuhide Doi

发明人： Naohiko Hirano ,  Kazuhide Doi

IPC分类号： H01L23/00 ,  H01L23/12 ,  H01L23/13 ,  H05K1/02 ,  H01L23/34

CPC分类号： H01L23/13 ,  H05K1/0271 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/3511 ,  H05K2201/09036 ,  H05K2201/09063 ,  H05K2201/10674

摘要： A semiconductor device includes a rectangular wiring substrate and a plurality of semiconductor elements having connecting electrodes such as projecting electrodes connected to the wiring substrate. Even though the wiring substrate is deformed, the semiconductor elements and connecting electrodes are prevented from being broken, thereby maintaining the reliability of the semiconductor device for a long period of time. A buffer region constituted by grooves is formed in that middle part of the undersurface of the rectangular wiring substrate which is located between both the long sides of the wiring substrate and between both the short sides thereof. The semiconductor elements are formed outside the buffer region. The connecting electrodes of the semiconductor elements are connected to a wiring pattern on the surface of the wiring substrate, with the result that the semiconductor elements are mounted on the wiring substrate. The deformation of the buffer region absorbs a deformation of that part of the wiring substrate which is located near the semiconductor elements mounted on the wiring substrate thereby to protect the semiconductor elements.

摘要翻译： 半导体器件包括矩形布线基板和多个具有诸如连接到布线基板的突出电极的连接电极的半导体元件。 即使布线基板变形，也可以防止半导体元件和连接电极的断裂，从而保持半导体器件的长时间的可靠性。 在矩形布线基板的下表面的位于布线基板的两个长边之间的两个短边之间的中间部分处形成有由凹槽构成的缓冲区域。 半导体元件形成在缓冲区的外部。 半导体元件的连接电极与布线基板的表面上的布线图形连接，结果半导体元件安装在布线基板上。 缓冲区域的变形吸收位于布线基板上的半导体元件附近的布线基板的那部分的变形，从而保护半导体元件。

公开(公告)号：US07235876B2

公开(公告)日：2007-06-26

申请号：US11516501

申请日：2006-09-07

申请人： Tomomi Okumura ,  Yoshitsugu Sakamoto ,  Naohiko Hirano ,  Kuniaki Mamitsu

发明人： Tomomi Okumura ,  Yoshitsugu Sakamoto ,  Naohiko Hirano ,  Kuniaki Mamitsu

IPC分类号： H01L23/10 ,  H01L23/34

CPC分类号： H01L23/051 ,  H01L23/492 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32057 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/83385 ,  H01L2224/83455 ,  H01L2224/83801 ,  H01L2224/92147 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/0132 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device includes: first and second metallic plates, each of which includes a heat radiation surface and an inner surface; a semiconductor element between the metallic plates; a block between the second metallic plate and the semiconductor element; a solder member between the second metallic plate and the block; and a resin mold. The heat radiation surface is exposed from the resin mold. The second metallic plate includes a groove for preventing the solder member from expanding outside of the block. The groove is disposed on the inner surface and disposed on an outer periphery of the block. The second metallic plate further includes an inner surface member on an inner surface of the groove. The inner surface member has a solder wettability, which is larger than a solder wettability of the block.

公开(公告)号：US06927167B2

公开(公告)日：2005-08-09

申请号：US10732376

申请日：2003-12-11

申请人： Yutaka Fukuda ,  Naohiko Hirano ,  Chikage Noritake ,  Shoji Miura

发明人： Yutaka Fukuda ,  Naohiko Hirano ,  Chikage Noritake ,  Shoji Miura

IPC分类号： H01L21/28 ,  H01L21/304 ,  H01L21/306 ,  H01L21/331 ,  H01L21/336 ,  H01L23/433 ,  H01L23/495 ,  H01L29/34 ,  H01L29/41 ,  H01L29/78 ,  H01L21/302

CPC分类号： H01L24/33 ,  H01L21/304 ,  H01L21/30604 ,  H01L23/4334 ,  H01L23/49562 ,  H01L24/32 ,  H01L24/48 ,  H01L29/34 ,  H01L29/66333 ,  H01L2224/05599 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for manufacturing a semiconductor device with a substrate having a device layer and a backside electrode is disclosed. Here, a surface roughness of the substrate is defined as a ratio between a substantial area and a projected area. The method includes polishing and wet-etching a backside surface of the substrate mechanically with using predetermined abrasive grains so that a surface roughness of the backside surface of the substrate becomes to be equal to or larger than 1.04, and forming the backside electrode on the backside surface of the substrate after polishing and wet-etching the backside surface of the substrate.

摘要翻译： 公开了一种具有具有器件层和背面电极的衬底的半导体器件的制造方法。 这里，基板的表面粗糙度被定义为实质面积和投影面积之间的比率。 该方法包括使用预定的磨粒机械地抛光和湿法蚀刻衬底的背面，使得衬底的背面的表面粗糙度等于或大于1.04，并且在背面形成背面电极 抛光后的基板的表面和湿法蚀刻基板的背面。

公开(公告)号：US20050167802A1

公开(公告)日：2005-08-04

申请号：US11019242

申请日：2004-12-23

申请人： Naohiko Hirano ,  Kuniaki Mamitsu

发明人： Naohiko Hirano ,  Kuniaki Mamitsu

IPC分类号： H01L23/40 ,  H01L21/28 ,  H01L21/44 ,  H01L21/50 ,  H01L21/60 ,  H01L23/02 ,  H01L23/34 ,  H01L23/433 ,  H01L23/488 ,  H01L23/492 ,  H01L25/07

CPC分类号： H01L24/33 ,  H01L23/4334 ,  H01L23/488 ,  H01L24/32 ,  H01L25/072 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/32258 ,  H01L2224/33181 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01068 ,  H01L2924/01082 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device includes first and second semiconductor elements, a first metal body attached to a first side of the semiconductor elements by a first solder portion, a second metal body attached to a second side of the semiconductor elements with a second solder portion, and a resin mold sealing the semiconductor elements, the first metal body and the second metal body by encapsulating them. In the semiconductor device having the second side as an element disposition surface, strain measurement caused by heat stress is maximum at the first solder portion among soldering portions of the semiconductor elements.

摘要翻译： 半导体器件包括第一和第二半导体元件，通过第一焊料部分附着到半导体元件的第一侧的第一金属体，用第二焊料部分附着到半导体元件的第二侧的第二金属体，以及 树脂模具通过封装半导体元件，第一金属体和第二金属体来密封。 在具有作为元件配置面的第二面的半导体器件中，在半导体元件的焊接部中的第一焊料部处，由热应力引起的应变测量最大。