-
公开(公告)号：US09559077B2
公开(公告)日：2017-01-31
申请号：US14521451
申请日：2014-10-22
CPC分类号： H01L23/49541 , H01L21/4828 , H01L21/561 , H01L21/563 , H01L23/3107 , H01L23/3135 , H01L23/3142 , H01L23/49503 , H01L23/49513 , H01L23/49575 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/30 , H01L24/32 , H01L24/33 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/85 , H01L24/92 , H01L24/96 , H01L24/97 , H01L25/0655 , H01L2224/11334 , H01L2224/11436 , H01L2224/1161 , H01L2224/119 , H01L2224/13005 , H01L2224/13082 , H01L2224/131 , H01L2224/1319 , H01L2224/1329 , H01L2224/13294 , H01L2224/133 , H01L2224/16245 , H01L2224/27334 , H01L2224/27436 , H01L2224/2761 , H01L2224/291 , H01L2224/2919 , H01L2224/2929 , H01L2224/29294 , H01L2224/293 , H01L2224/30131 , H01L2224/3201 , H01L2224/32014 , H01L2224/32245 , H01L2224/32257 , H01L2224/32258 , H01L2224/3301 , H01L2224/33505 , H01L2224/48091 , H01L2224/48106 , H01L2224/48137 , H01L2224/48247 , H01L2224/48465 , H01L2224/48471 , H01L2224/73204 , H01L2224/73257 , H01L2224/73265 , H01L2224/81192 , H01L2224/81201 , H01L2224/81447 , H01L2224/81455 , H01L2224/81801 , H01L2224/8185 , H01L2224/83104 , H01L2224/83192 , H01L2224/83201 , H01L2224/83385 , H01L2224/83447 , H01L2224/83455 , H01L2224/83801 , H01L2224/8385 , H01L2224/83851 , H01L2224/83907 , H01L2224/85205 , H01L2224/85207 , H01L2224/92 , H01L2224/9205 , H01L2224/9222 , H01L2224/92227 , H01L2224/92247 , H01L2924/00014 , H01L2924/01026 , H01L2924/01028 , H01L2924/1715 , H01L2924/17747 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/83 , H01L2224/85 , H01L2924/0665 , H01L2924/014 , H01L2924/0782 , H01L2224/81 , H01L2224/114 , H01L2924/0781 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method for forming a packaged semiconductor device includes attaching a first major surface of a semiconductor die to a plurality of protrusions extending from a package substrate. A top surface of each protrusion has a die attach material, and the plurality of protrusions define an open region between the first major surface of the semiconductor die and the package substrate. Interconnects are formed between a second major surface of the semiconductor die and the package substrate in which the second major surface opposite the first major surface. An encapsulant material is formed over the semiconductor die and the interconnects.
摘要翻译： 一种形成封装半导体器件的方法包括将半导体管芯的第一主表面附接到从封装衬底延伸的多个突起。 每个突起的顶表面具有管芯附接材料，并且多个突起限定半导体管芯的第一主表面和封装衬底之间的开放区域。 在半导体管芯的第二主表面和与第一主表面相对的第二主表面的封装衬底之间形成互连。 在半导体管芯和互连件之上形成密封剂材料。
-
公开(公告)号：US09590063B2
公开(公告)日：2017-03-07
申请号：US14576537
申请日：2014-12-19
发明人： Rama I. Hegde
IPC分类号： H01L21/3205 , H01L29/423 , H01L29/51 , H01L21/02 , H01L21/285 , H01L21/28
CPC分类号： H01L29/42364 , C23C16/405 , C23C16/45534 , H01L21/02181 , H01L21/0228 , H01L21/28194 , H01L21/28556 , H01L29/517
摘要： A method of forming a semiconductor device (100) includes depositing a metal oxide (104) over the substrate (102). The depositing includes combining a first metal and oxygen to form the metal oxide having grains and further adding a catalyst during the combining. The catalyst causes the grains to be bigger than would occur in the absence of the catalyst. A conductive layer (202) is formed over the metal oxide.
摘要翻译： 形成半导体器件（100）的方法包括在衬底（102）上沉积金属氧化物（104）。 沉积包括组合第一金属和氧以形成具有晶粒的金属氧化物，并且在组合期间进一步加入催化剂。 催化剂使得颗粒大于在不存在催化剂的情况下会发生的。 导电层（202）形成在金属氧化物的上方。
-
公开(公告)号：US09337164B2
公开(公告)日：2016-05-10
申请号：US14525855
申请日：2014-10-28
发明人： Rama I. Hegde
IPC分类号： H01L23/48 , H01L23/00 , H01L23/495 , H01L21/48
CPC分类号： H01L24/45 , H01L21/4821 , H01L21/4846 , H01L23/49548 , H01L23/49582 , H01L23/49586 , H01L24/32 , H01L24/43 , H01L24/48 , H01L24/73 , H01L2224/32245 , H01L2224/43 , H01L2224/45147 , H01L2224/45565 , H01L2224/45573 , H01L2224/45647 , H01L2224/45666 , H01L2224/45681 , H01L2224/45687 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/48465 , H01L2224/73265 , H01L2924/12042 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/04941 , H01L2924/04953 , H01L2924/013 , H01L2924/0104 , H01L2924/01072 , H01L2924/00012
摘要： A coating layer for use in copper integrated circuit interconnect and other conductive structures hinders and decreases oxide growth on surfaces of such conductive structures. The coating layer includes an amorphous copper containing layer deposited on a crystalline copper substrate, such as utilized for a lead frame and a bonding wire. Additional amorphous layers may be interposed between the amorphous copper containing layer and the copper substrate, such as an amorphous tantalum nitride layer and an amorphous titanium nitride layer.
摘要翻译： 用于铜集成电路互连和其它导电结构的涂层阻碍并减少这种导电结构表面上的氧化物生长。 涂层包括沉积在结晶铜基底上的非晶态含铜层，例如用于引线框架和接合线。 可以在非晶态含铜层和铜基板之间插入附加非晶层，例如非晶氮化钽层和无定形氮化钛层。
-
公开(公告)号：US20150214177A1
公开(公告)日：2015-07-30
申请号：US14525855
申请日：2014-10-28
发明人： Rama I. Hegde
IPC分类号： H01L23/00 , H01L21/48 , H01L23/495
CPC分类号： H01L24/45 , H01L21/4821 , H01L21/4846 , H01L23/49548 , H01L23/49582 , H01L23/49586 , H01L24/32 , H01L24/43 , H01L24/48 , H01L24/73 , H01L2224/32245 , H01L2224/43 , H01L2224/45147 , H01L2224/45565 , H01L2224/45573 , H01L2224/45647 , H01L2224/45666 , H01L2224/45681 , H01L2224/45687 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/48465 , H01L2224/73265 , H01L2924/12042 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/04941 , H01L2924/04953 , H01L2924/013 , H01L2924/0104 , H01L2924/01072 , H01L2924/00012
摘要： A coating layer for use in copper integrated circuit interconnect and other conductive structures hinders and decreases oxide growth on surfaces of such conductive structures. The coating layer includes an amorphous copper containing layer deposited on a crystalline copper substrate, such as utilized for a lead frame and a bonding wire. Additional amorphous layers may be interposed between the amorphous copper containing layer and the copper substrate, such as an amorphous tantalum nitride layer and an amorphous titanium nitride layer.
摘要翻译： 用于铜集成电路互连和其它导电结构的涂层阻碍并减少这种导电结构表面上的氧化物生长。 涂层包括沉积在结晶铜基底上的非晶态含铜层，例如用于引线框架和接合线。 可以在非晶态含铜层和铜基板之间插入附加非晶层，例如非晶氮化钽层和无定形氮化钛层。
-
-
-
搜索结果
4 条记录 (耗时 0.012 秒)
