公开(公告)号：US07489037B2

公开(公告)日：2009-02-10

申请号：US11373693

申请日：2006-03-10

申请人： Feng-Lung Chien ,  Chao-Dung Suo ,  Yi-Hsin Chen

发明人： Feng-Lung Chien ,  Chao-Dung Suo ,  Yi-Hsin Chen

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L24/12 ,  H01L23/3114 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05569 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13021 ,  H01L2224/13099 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/013

摘要： A semiconductor device and a fabrication method thereof are proposed. A first dielectric layer is formed on a semiconductor substrate having at least one bond pad, wherein the first dielectric layer has a first opening for exposing the bond pad and a second opening at a predetermined position for redistribution. A first metallic layer is applied on the first dielectric layer and in the first and second openings. A second metallic layer and a third metallic layer are formed on the first metallic layer at positions corresponding to the first and second openings, respectively. A second dielectric layer and a solder bump are formed on the second and third metallic layers, respectively. The second metallic layer can assure electrical quality of the first metallic layer corresponding to the first opening without having an electrical break of the first metallic layer for redistribution.

摘要翻译： 提出了一种半导体器件及其制造方法。 第一电介质层形成在具有至少一个接合焊盘的半导体衬底上，其中第一介电层具有用于暴露接合焊盘的第一开口和用于再分配的预定位置的第二开口。 第一金属层被施加在第一介电层上和第一和第二开口中。 第二金属层和第三金属层分别在对应于第一和第二开口的位置处形成在第一金属层上。 在第二和第三金属层上分别形成第二电介质层和焊料凸块。 第二金属层可以确保对应于第一开口的第一金属层的电气质量，而不会导致第一金属层的电断裂用于再分配。

公开(公告)号：US20060226542A1

公开(公告)日：2006-10-12

申请号：US11373693

申请日：2006-03-10

申请人： Feng-Lung Chien ,  Chao-Dung Suo ,  Yi-Hsin Chen

发明人： Feng-Lung Chien ,  Chao-Dung Suo ,  Yi-Hsin Chen

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L24/12 ,  H01L23/3114 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05569 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13021 ,  H01L2224/13099 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/013

摘要： A semiconductor device and a fabrication method thereof are proposed. A first dielectric layer is formed on a semiconductor substrate having at least one bond pad, wherein the first dielectric layer has a first opening for exposing the bond pad and a second opening at a predetermined position for redistribution. A first metallic layer is applied on the first dielectric layer and in the first and second openings. A second metallic layer and a third metallic layer are formed on the first metallic layer at positions corresponding to the first and second openings, respectively. A second dielectric layer and a solder bump are formed on the second and third metallic layers, respectively. The second metallic layer can assure electrical quality of the first metallic layer corresponding to the first opening without having an electrical break of the first metallic layer for redistribution.

公开(公告)号：US20120280384A1

公开(公告)日：2012-11-08

申请号：US13167086

申请日：2011-06-23

申请人： Yi-Hung Lin ,  Meng-Tsung Lee ,  Sui-An Kao ,  Yi-Hsin Chen ,  Feng-Lung Chien

发明人： Yi-Hung Lin ,  Meng-Tsung Lee ,  Sui-An Kao ,  Yi-Hsin Chen ,  Feng-Lung Chien

IPC分类号： H01L23/48 ,  H01L21/283

CPC分类号： H01L24/11 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/039 ,  H01L2224/03901 ,  H01L2224/03903 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/0556 ,  H01L2224/05564 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/116 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0132 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2224/0347 ,  H01L2224/1161 ,  H01L2224/05552

摘要： A fabrication method of a semiconductor structure includes providing a chip having at least an electrode pad, forming a titanium layer on the electrode pad, forming a dielectric layer on the chip and a portion of the titanium layer, forming a copper layer on the dielectric layer and the titanium layer, forming a conductive pillar on the copper layer corresponding in position to the titanium layer, and removing a portion of the copper layer that is not covered by the conductive pillar. When the portion of the copper layer is removed by etching, undercutting of the titanium layer is avoided since the titanium layer is covered by the dielectric layer, thereby providing an improved support for the conductive pillar to increase product reliability.

摘要翻译： 半导体结构的制造方法包括提供至少具有电极焊盘的芯片，在电极焊盘上形成钛层，在芯片上形成电介质层和钛层的一部分，在电介质层上形成铜层 和钛层，在与铜层相对应的铜层上形成导电柱，并除去未被导电柱覆盖的铜层的一部分。 当通过蚀刻去除铜层的部分时，由于钛层被电介质层覆盖，所以避免了钛层的底切，从而为导电柱提供改进的支撑以提高产品的可靠性。

公开(公告)号：US20120126397A1

公开(公告)日：2012-05-24

申请号：US12987571

申请日：2011-01-10

申请人： Feng-Lung Chien ,  Yi-Hsin Chen ,  Kuei-Hsiao Kuo

发明人： Feng-Lung Chien ,  Yi-Hsin Chen ,  Kuei-Hsiao Kuo

IPC分类号： H01L23/498 ,  B05D5/12 ,  B23K1/20

CPC分类号： B23K1/0016 ,  B23K3/0623 ,  B23K3/08 ,  B23K2101/40 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/93 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/036 ,  H01L2224/03849 ,  H01L2224/0391 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/051 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11502 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/93 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/35121 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/00

摘要： A semiconductor substrate includes a substrate having plurality of electrical contact pads formed thereon, a first insulating protective layer formed on the substrate that exposes the electrical contact pads, a plurality of metal layers formed on the exposed electrical contact pads, a second insulating protective layer formed on the first insulating protective layer that exposes a portion of the metal layers, and a plurality of solder bumps formed on the exposed metal layers having copper. Through the second insulating protective layer covering a portion of the metal layers, the solder bumps are prevented from falling off or crack when the semiconductor substrate is under a temperature test.

摘要翻译： 半导体衬底包括其上形成有多个电接触焊盘的衬底，形成在衬底上的暴露电接触焊盘的第一绝缘保护层，形成在暴露的电接触焊盘上的多个金属层，形成的第二绝缘保护层 在露出一部分金属层的第一绝缘保护层上，以及形成在具有铜的暴露的金属层上的多个焊料凸点。 通过覆盖金属层的一部分的第二绝缘保护层，当半导体衬底处于温度测试时，防止焊料凸起脱落或破裂。

公开(公告)号：US08866293B2

公开(公告)日：2014-10-21

申请号：US13167086

申请日：2011-06-23

申请人： Yi-Hung Lin ,  Meng-Tsung Lee ,  Sui-An Kao ,  Yi-Hsin Chen ,  Feng-Lung Chien

发明人： Yi-Hung Lin ,  Meng-Tsung Lee ,  Sui-An Kao ,  Yi-Hsin Chen ,  Feng-Lung Chien

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L24/11 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/039 ,  H01L2224/03901 ,  H01L2224/03903 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/0556 ,  H01L2224/05564 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/116 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0132 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2224/0347 ,  H01L2224/1161 ,  H01L2224/05552

摘要： A semiconductor structure includes a semiconductor chip having at least an electrode pad, a first metal layer formed on the electrode pad, a second metal layer completely formed on and in contact with the first metal layer, and a conductive pillar disposed on the second metal layer, where a material of the first metal layer is different from a material of the second metal layer, the first metal layer has a first distribution-projected area larger than a second distribution projected-area of the conductive pillar, and the second metal layer has a third distribution-projected area that is the same as the second distribution-projected area of the conductive pillar.

摘要翻译： 半导体结构包括具有至少电极焊盘，形成在电极焊盘上的第一金属层，完全形成在第一金属层上并与第一金属层接触的第二金属层的半导体芯片和设置在第二金属层上的导电柱 其中，所述第一金属层的材料与所述第二金属层的材料不同，所述第一金属层具有大于所述导电柱的第二分布投影面积的第一分布投影面积，并且所述第二金属层具有 与导电柱的第二分布投影面积相同的第三分布投影面积。

公开(公告)号：US20060094224A1

公开(公告)日：2006-05-04

申请号：US11251901

申请日：2005-10-18

申请人： Min-Lung Huang ,  Yi-Hsin Chen ,  Jia-Bin Chen

发明人： Min-Lung Huang ,  Yi-Hsin Chen ,  Jia-Bin Chen

IPC分类号： H01L21/44

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05671 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1357 ,  H01L2224/13611 ,  H01L2924/00013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/13099

摘要： A bumping process is provided. The bumping process comprises the steps of: firstly, providing a wafer; next forming an under bump metallurgy (UBM) on the active surface of the wafer; then, forming a photo-resist layer on the active surface of the wafer and forming at least an opening in the photo-resist layer; then, sequentially forming a copper post, a barrier and a copper layer; then removing the photo-resist layer; finally reflowing the solder layer in the opening. The barrier layer is made of the materials such as nickel, lest the copper post and the solder layer might contact directly, causing the copper to diffuse fast and lose accordingly. Therefore, the quality of bumping process and structure can be enhanced according to the present invention.

摘要翻译： 提供碰撞过程。 碰撞过程包括以下步骤：首先提供晶片; 接下来在晶片的有源表面上形成凸块下金属（UBM）; 然后在晶片的有源表面上形成光致抗蚀剂层，并形成光致抗蚀剂层中的至少一个开口; 然后顺序地形成铜柱，阻挡层和铜层; 然后除去光致抗蚀剂层; 最后在开口中回流焊料层。 阻挡层由诸如镍的材料制成，以免铜柱和焊料层直接接触，导致铜快速扩散并相应地损失。 因此，根据本发明，可以提高碰撞过程和结构的质量。

公开(公告)号：US5970807A

公开(公告)日：1999-10-26

申请号：US703255

申请日：1996-08-26

申请人： Hwa-Ching Hsu ,  Wan-Lai Chen ,  Yi-Hsin Chen

发明人： Hwa-Ching Hsu ,  Wan-Lai Chen ,  Yi-Hsin Chen

IPC分类号： H01L21/00 ,  H01L21/677 ,  G01M19/00 ,  G01B5/16 ,  G01D21/00

CPC分类号： H01L21/67265 ,  H01L21/67781

摘要： A method and apparatus to gage the spacing between a plurality of handling elements used for transferring planar objects into and out of holding receptacles in a semiconductor process. The handling tweezers are moved to a checking location and fit interleaved with the gage apparatus. If the handling tweezers do not fit, the tweezers are moved to an accessible maintenance location for alignment and recalibration enabling its use for transferring semiconductor wafers to and from wafer holding receptacles in a chemical vapor deposition vertical diffusion furnace.

摘要翻译： 一种用于在半导体工艺中计量用于将平面物体输入和移出保持容器的多个处理元件之间的间距的方法和装置。 处理镊子被移动到检查位置并且与计量装置交错配合。 如果处理镊子不适合，则将镊子移动到可访问的维护位置以进行对准和重新校准，以使其能够在化学气相沉积垂直扩散炉中将半导体晶片传送到晶片保持容器和/或从晶片保持容器转移。

公开(公告)号：US20060094226A1

公开(公告)日：2006-05-04

申请号：US11229556

申请日：2005-09-20

申请人： Min-Lung Huang ,  Yi-Hsin Chen ,  Jia-Bin Chen

发明人： Min-Lung Huang ,  Yi-Hsin Chen ,  Jia-Bin Chen

IPC分类号： H01L21/44

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1147 ,  H01L2224/11902 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/13099

摘要： A bumping process is provided as following: at first, providing a wafer, then forming a first photo-resist layer on a active surface of the wafer and forming at least a first opening on the first photo-resist layer; and forming a copper pillar in the first opening; then forming a second photo-resist layer on the first photo-resist layer and forming at least a second opening on the second photo-resist layer; finally forming a solder layer in the second opening to attach the solder layer on the copper pillar, and removing the first and second photo-resist layer.

摘要翻译： 提供如下碰撞过程：首先，提供晶片，然后在晶片的有效表面上形成第一光致抗蚀剂层，并在第一光致抗蚀剂层上形成至少第一开口; 并在所述第一开口中形成铜柱; 然后在第一光致抗蚀剂层上形成第二光致抗蚀剂层，并在第二光致抗蚀剂层上形成至少第二开口; 最后在第二开口中形成焊料层，以将焊料层附着在铜柱上，并除去第一和第二光致抗蚀剂层。

公开(公告)号：US20060087034A1

公开(公告)日：2006-04-27

申请号：US11236196

申请日：2005-09-27

申请人： Min-Lung Huang ,  Yi-Hsin Chen ,  Jia-Bin Chen

发明人： Min-Lung Huang ,  Yi-Hsin Chen ,  Jia-Bin Chen

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2224/1147 ,  H01L2224/11902 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2924/00013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/13099

摘要： A bumping process includes the steps of: firstly, providing a wafer; forming a first photo-resist layer on a active surface of the wafer and forming at least a first opening on the first photo-resist layer; next, forming a first copper pillar in the first opening; next, forming a second photo-resist layer on the first photo-resist layer and forming at least a second opening on the second photo-resist layer, wherein the second opening smaller than the first opening so that a portion of the surface of the first copper pillar is exposed in the second opening; then, forming a second copper pillar in the second opening; finally, forming a solder layer on the second copper pillar; and removing the first and second photo-resist layers.

摘要翻译： 碰撞过程包括以下步骤：首先，提供晶片; 在所述晶片的有效表面上形成第一光致抗蚀剂层，并且在所述第一光致抗蚀剂层上形成至少第一开口; 接下来，在第一开口中形成第一铜柱; 接下来，在第一光致抗蚀剂层上形成第二光致抗蚀剂层，并在第二光刻胶层上形成至少第二开口，其中第二开口小于第一开口，使得第一光刻胶层的第一光刻胶表面的一部分 铜柱在第二个开口处露出; 然后在第二开口中形成第二铜柱; 最后，在第二铜柱上形成焊料层; 并除去第一和第二光致抗蚀剂层。

公开(公告)号：US11525384B2

公开(公告)日：2022-12-13

申请号：US16780359

申请日：2020-02-03

申请人： Wensheng Zhang ,  Rohit Paranjpe ,  Yi-Hsin Chen ,  Kanwerdip Singh

发明人： Wensheng Zhang ,  Rohit Paranjpe ,  Yi-Hsin Chen ,  Kanwerdip Singh

IPC分类号： F16B5/02 ,  F01N13/18 ,  F16B43/00 ,  F16B39/24 ,  F16B1/00

摘要： A bolted joint for coupling two components that undergo thermal expansion and contraction includes a bolt having a head and a stem, the bolt configured to provide a clamping force between the two components. A first washer having a thermal resistant, low friction coating is configured to be disposed between one of the two components and the bolt head to enable the one component to slide relative to the bolt during the thermal expansion and contraction, while maintaining the clamping force, to facilitate preventing bending or shearing of the bolt.