公开(公告)号：US06753609B2

公开(公告)日：2004-06-22

申请号：US09861425

申请日：2001-05-18

申请人： Feng-Lung Chien ,  Randy H. Y. Lo ,  Chun-chi Ke

发明人： Feng-Lung Chien ,  Randy H. Y. Lo ,  Chun-chi Ke

IPC分类号： H01L2348

CPC分类号： H01L24/11 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/013

摘要： A method is proposed for forming circuit probing (CP) contact points on fine pitch peripheral bond pads (PBP) on a flip chip for the purpose of facilitating peripheral circuit probing of the internal circuitry of the flip chip. The proposed method is characterized in the forming of a dual-layer NiV/Cu metallization structure, rather than a triple-layer Al/NiV/Cu metallization structure, over each aluminum-based PBP, which includes a bottom layer of nickel-vanadium (NiV) deposited over the aluminum-based PBP and an upper layer of copper (Cu) deposited over the nickel-vanadium layer. When low-resolution photolithographic and etching equipment is used for photoresist mask definition for selective removal of the NiV/Cu metallization structure, the resulted photoresist masking can be misaligned to the PBP. However, since no aluminum layer is included in the metallization structure, a Cu/NiV specific etchant would only etch away the copper layer and the nickel-vanadium layer but not the aluminum-based PBP, thus leaving the unmasked portion of the aluminum-based PBP intact.

摘要翻译： 提出了一种用于在倒装芯片上的细间距外围接合焊盘（PBP）上形成电路探测（CP）接触点的方法，其目的在于便于倒装芯片的内部电路的外围电路探测。 所提出的方法的特征在于在每个基于铝的PBP上形成双层NiV / Cu金属化结构而不是三层Al / NiV / Cu金属化结构，其包括镍 - 钒的底层（ NiV）沉积在铝基PBP上并沉积在镍 - 钒层上的铜（Cu）上层。 当低分辨率光刻和蚀刻设备用于光刻胶掩模定义以选择性去除NiV / Cu金属化结构时，所得到的光刻胶掩模可能不对准PBP。 然而，由于在金属化结构中不包括铝层，所以Cu / NiV特定蚀刻剂将仅蚀刻掉铜层和镍 - 钒层而不是铝基PBP，从而留下铝基的未掩模部分 PBP完好无损。

公开(公告)号：US06258705B1

公开(公告)日：2001-07-10

申请号：US09642319

申请日：2000-08-21

申请人： Feng-Lung Chien ,  Randy H.Y. Lo ,  Chun-chi Ke

发明人： Feng-Lung Chien ,  Randy H.Y. Lo ,  Chun-chi Ke

IPC分类号： H01L2144

CPC分类号： H01L24/11 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/013

摘要： A method is proposed for forming circuit probing (CP) contact points on fine pitch peripheral bond pads (PBP) on a flip chip for the purpose of facilitating peripheral circuit probing of the internal circuitry of the flip chip. The proposed method is characterized in the forming of a dual-layer NiV/Cu metallization structure, rather than a triple-layer Al/NiV/Cu metallization structure, over each aluminum-based PBP, which includes a bottom layer of nickel-vanadium (NiV) deposited over the aluminum-based PBP and an upper layer of copper (Cu) deposited over the nickel-vanadium layer. When low-resolution photolithographic and etching equipment is used for photoresist mask definition for selective removal of the NiV/Cu metallization structure, the resulted photoresist masking can be misaligned to the PBP. However, since no aluminum layer is included in the metallization structure, a Cu/NiV specific etchant would only etch away the copper layer and the nickel-vanadium layer but not the aluminum-based PBP, thus leaving the unmasked portion of the aluminum-based PBP intact.

摘要翻译： 提出了一种用于在倒装芯片上的细间距外围接合焊盘（PBP）上形成电路探测（CP）接触点的方法，其目的在于便于倒装芯片的内部电路的外围电路探测。 所提出的方法的特征在于在每个基于铝的PBP上形成双层NiV / Cu金属化结构而不是三层Al / NiV / Cu金属化结构，其包括镍 - 钒的底层（ NiV）沉积在铝基PBP上并沉积在镍 - 钒层上的铜（Cu）上层。 当低分辨率光刻和蚀刻设备用于光刻胶掩模定义以选择性去除NiV / Cu金属化结构时，所得到的光刻胶掩模可能不对准PBP。 然而，由于在金属化结构中不包括铝层，所以Cu / NiV特定蚀刻剂将仅蚀刻掉铜层和镍 - 钒层而不是铝基PBP，从而留下铝基的未掩模部分 PBP完好无损。

公开(公告)号：US20120126397A1

公开(公告)日：2012-05-24

申请号：US12987571

申请日：2011-01-10

申请人： Feng-Lung Chien ,  Yi-Hsin Chen ,  Kuei-Hsiao Kuo

发明人： Feng-Lung Chien ,  Yi-Hsin Chen ,  Kuei-Hsiao Kuo

IPC分类号： H01L23/498 ,  B05D5/12 ,  B23K1/20

CPC分类号： B23K1/0016 ,  B23K3/0623 ,  B23K3/08 ,  B23K2101/40 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/93 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/036 ,  H01L2224/03849 ,  H01L2224/0391 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/051 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11502 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/93 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/35121 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/00

摘要： A semiconductor substrate includes a substrate having plurality of electrical contact pads formed thereon, a first insulating protective layer formed on the substrate that exposes the electrical contact pads, a plurality of metal layers formed on the exposed electrical contact pads, a second insulating protective layer formed on the first insulating protective layer that exposes a portion of the metal layers, and a plurality of solder bumps formed on the exposed metal layers having copper. Through the second insulating protective layer covering a portion of the metal layers, the solder bumps are prevented from falling off or crack when the semiconductor substrate is under a temperature test.

摘要翻译： 半导体衬底包括其上形成有多个电接触焊盘的衬底，形成在衬底上的暴露电接触焊盘的第一绝缘保护层，形成在暴露的电接触焊盘上的多个金属层，形成的第二绝缘保护层 在露出一部分金属层的第一绝缘保护层上，以及形成在具有铜的暴露的金属层上的多个焊料凸点。 通过覆盖金属层的一部分的第二绝缘保护层，当半导体衬底处于温度测试时，防止焊料凸起脱落或破裂。

公开(公告)号：US07341949B2

公开(公告)日：2008-03-11

申请号：US10861556

申请日：2004-06-04

申请人： Feng-Lung Chien ,  Huang-Chuan Chang ,  Chun-Sheng Ho

发明人： Feng-Lung Chien ,  Huang-Chuan Chang ,  Chun-Sheng Ho

IPC分类号： H01L21/302

CPC分类号： H01L24/11 ,  H01L24/02 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11502 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00

摘要： A process for forming a lead-free bump on an electronic component includes preparing the electronic component with at least one bond pad and a passivation layer formed thereon; forming an under bump metallurgy (UBM) structure on the passivation layer and the bond pad; applying a photoresist over the passivation layer, the photoresist having at least one opening corresponding to the bond pad; depositing a thick copper layer (about 1 to 10 μm thick) in the opening by electroplating; applying a copper-free or low-copper-content solder material on the copper layer; and performing a reflowing procedure under a suitable reflow temperature profile to allow copper ions to diffuse from the copper layer to the solder material so as to form the lead-free bump. This increases the copper content in the solder material but not raising the reflow temperature profile, thereby preventing deterioration of the photoresist due to over heat.

摘要翻译： 用于在电子部件上形成无铅凸块的工艺包括：制备具有至少一个焊盘和形成在其上的钝化层的电子部件; 在钝化层和接合焊盘上形成凸块下金属（UBM）结构; 在所述钝化层上施加光致抗蚀剂，所述光致抗蚀剂具有对应于所述接合焊盘的至少一个开口; 通过电镀在开口中沉积厚铜层（约1〜10μm厚）; 在铜层上施加无铜或低铜含量的焊料; 并在合适的回流温度曲线下进行回流过程，以使铜离子从铜层扩散到焊料材料，从而形成无铅凸点。 这增加了焊料材料中的铜含量，但不会提高回流温度曲线，从而防止由于过热引起的光致抗蚀剂的劣化。

公开(公告)号：US06348401B1

公开(公告)日：2002-02-19

申请号：US09709908

申请日：2000-11-10

申请人： Chih-Shun Chen ,  Chao-Dung Suo ,  Jui-Meng Jao ,  Ke-Chuan Yang ,  Feng-Lung Chien

发明人： Chih-Shun Chen ,  Chao-Dung Suo ,  Jui-Meng Jao ,  Ke-Chuan Yang ,  Feng-Lung Chien

IPC分类号： H01L2144

CPC分类号： H01L24/05 ,  H01L24/02 ,  H01L24/03 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11502 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/11901 ,  H01L2224/131 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H05K3/3473 ,  H05K3/3484 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/29099 ,  H01L2224/05552 ,  H01L2224/1146

摘要： A solder-pump fabrication method is proposed, which is used for the fabrication of solder bumps with high coplanarity over a semiconductor chip for flip-chip application. The proposed solder-bump fabrication method is characterized in the use of a two-step solder-bump fabrication process, including a first step of electroplating solder over UBM (Under Bump Metallization) pads to a controlled height still below the topmost surface of the mask, and a second step of screen-printing solder paste over the electroplated solder layer. The combined structure of the electroplated solder layer and the printed solder layer is then reflowed to form the desired solder bump. Since the proposed solder-bump fabrication method allows the solder material electroplated and printed over the UBM pads to be confined within the mask openings and never exceed the topmost surface of the mask, the resulted solder bumps would not be bridged to neighboring ones. Moreover, the proposed solder-bump fabrication method allows all the resulted solder bumps to be substantially equally sized to achieve high coplanarity.

摘要翻译： 提出了一种焊料泵制造方法，其用于在用于倒装芯片的半导体芯片上制造具有高共面性的焊料凸块。 所提出的焊料凸点制造方法的特征在于使用两步骤焊料凸块制造工艺，其包括将UBM（低于Bump金属化）焊盘上的焊料电镀到仍然低于掩模的最上表面的受控高度的第一步骤 以及在电镀焊料层上丝网印刷焊膏的第二步骤。 然后将电镀焊料层和印刷焊料层的组合结构回流以形成所需的焊料凸点。 由于所提出的焊料凸点制造方法允许在UBM焊盘上电镀和印刷的焊料材料被限制在掩模开口内，并且不会超过掩模的最上表面，所以产生的焊料凸点不会被桥接到相邻焊盘。 此外，所提出的焊料凸块制造方法允许所有所得到的焊料凸块基本相同的尺寸以实现高共面性。

公开(公告)号：US20120280384A1

公开(公告)日：2012-11-08

申请号：US13167086

申请日：2011-06-23

申请人： Yi-Hung Lin ,  Meng-Tsung Lee ,  Sui-An Kao ,  Yi-Hsin Chen ,  Feng-Lung Chien

发明人： Yi-Hung Lin ,  Meng-Tsung Lee ,  Sui-An Kao ,  Yi-Hsin Chen ,  Feng-Lung Chien

IPC分类号： H01L23/48 ,  H01L21/283

CPC分类号： H01L24/11 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/039 ,  H01L2224/03901 ,  H01L2224/03903 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/0556 ,  H01L2224/05564 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/116 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0132 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2224/0347 ,  H01L2224/1161 ,  H01L2224/05552

摘要： A fabrication method of a semiconductor structure includes providing a chip having at least an electrode pad, forming a titanium layer on the electrode pad, forming a dielectric layer on the chip and a portion of the titanium layer, forming a copper layer on the dielectric layer and the titanium layer, forming a conductive pillar on the copper layer corresponding in position to the titanium layer, and removing a portion of the copper layer that is not covered by the conductive pillar. When the portion of the copper layer is removed by etching, undercutting of the titanium layer is avoided since the titanium layer is covered by the dielectric layer, thereby providing an improved support for the conductive pillar to increase product reliability.

摘要翻译： 半导体结构的制造方法包括提供至少具有电极焊盘的芯片，在电极焊盘上形成钛层，在芯片上形成电介质层和钛层的一部分，在电介质层上形成铜层 和钛层，在与铜层相对应的铜层上形成导电柱，并除去未被导电柱覆盖的铜层的一部分。 当通过蚀刻去除铜层的部分时，由于钛层被电介质层覆盖，所以避免了钛层的底切，从而为导电柱提供改进的支撑以提高产品的可靠性。

公开(公告)号：US07489037B2

公开(公告)日：2009-02-10

申请号：US11373693

申请日：2006-03-10

申请人： Feng-Lung Chien ,  Chao-Dung Suo ,  Yi-Hsin Chen

发明人： Feng-Lung Chien ,  Chao-Dung Suo ,  Yi-Hsin Chen

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L24/12 ,  H01L23/3114 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05569 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13021 ,  H01L2224/13099 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/013

摘要： A semiconductor device and a fabrication method thereof are proposed. A first dielectric layer is formed on a semiconductor substrate having at least one bond pad, wherein the first dielectric layer has a first opening for exposing the bond pad and a second opening at a predetermined position for redistribution. A first metallic layer is applied on the first dielectric layer and in the first and second openings. A second metallic layer and a third metallic layer are formed on the first metallic layer at positions corresponding to the first and second openings, respectively. A second dielectric layer and a solder bump are formed on the second and third metallic layers, respectively. The second metallic layer can assure electrical quality of the first metallic layer corresponding to the first opening without having an electrical break of the first metallic layer for redistribution.

摘要翻译： 提出了一种半导体器件及其制造方法。 第一电介质层形成在具有至少一个接合焊盘的半导体衬底上，其中第一介电层具有用于暴露接合焊盘的第一开口和用于再分配的预定位置的第二开口。 第一金属层被施加在第一介电层上和第一和第二开口中。 第二金属层和第三金属层分别在对应于第一和第二开口的位置处形成在第一金属层上。 在第二和第三金属层上分别形成第二电介质层和焊料凸块。 第二金属层可以确保对应于第一开口的第一金属层的电气质量，而不会导致第一金属层的电断裂用于再分配。

公开(公告)号：US20060226542A1

公开(公告)日：2006-10-12

申请号：US11373693

申请日：2006-03-10

申请人： Feng-Lung Chien ,  Chao-Dung Suo ,  Yi-Hsin Chen

发明人： Feng-Lung Chien ,  Chao-Dung Suo ,  Yi-Hsin Chen

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L24/12 ,  H01L23/3114 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05569 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13021 ,  H01L2224/13099 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/013

摘要： A semiconductor device and a fabrication method thereof are proposed. A first dielectric layer is formed on a semiconductor substrate having at least one bond pad, wherein the first dielectric layer has a first opening for exposing the bond pad and a second opening at a predetermined position for redistribution. A first metallic layer is applied on the first dielectric layer and in the first and second openings. A second metallic layer and a third metallic layer are formed on the first metallic layer at positions corresponding to the first and second openings, respectively. A second dielectric layer and a solder bump are formed on the second and third metallic layers, respectively. The second metallic layer can assure electrical quality of the first metallic layer corresponding to the first opening without having an electrical break of the first metallic layer for redistribution.

公开(公告)号：US20050042872A1

公开(公告)日：2005-02-24

申请号：US10861556

申请日：2004-06-04

申请人： Feng-Lung Chien ,  Huang-Chuan Chang ,  Chun-Sheng Ho

发明人： Feng-Lung Chien ,  Huang-Chuan Chang ,  Chun-Sheng Ho

IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L21/60 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/11 ,  H01L24/02 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11502 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00

摘要： A process for forming a lead-free bump on an electronic component includes preparing the electronic component with at least one bond pad and a passivation layer formed thereon; forming an under bump metallurgy (UBM) structure on the passivation layer and the bond pad; applying a photoresist over the passivation layer, the photoresist having at least one opening corresponding to the bond pad; depositing a thick copper layer (about 1 to 10 μm thick) in the opening by electroplating; applying a copper-free or low-copper-content solder material on the copper layer; and performing a reflowing procedure under a suitable reflow temperature profile to allow copper ions to diffuse from the copper layer to the solder material so as to form the lead-free bump. This increases the copper content in the solder material but not raising the reflow temperature profile, thereby preventing deterioration of the photoresist due to over heat.

摘要翻译： 用于在电子部件上形成无铅凸块的工艺包括：制备具有至少一个焊盘和形成在其上的钝化层的电子部件; 在钝化层和接合焊盘上形成凸块下金属（UBM）结构; 在所述钝化层上施加光致抗蚀剂，所述光致抗蚀剂具有对应于所述接合焊盘的至少一个开口; 通过电镀在开口中沉积厚铜层（约1〜10μm厚）; 在铜层上施加无铜或低铜含量的焊料; 并在合适的回流温度曲线下进行回流过程，以使铜离子从铜层扩散到焊料材料，从而形成无铅凸点。 这增加了焊料材料中的铜含量，但不会提高回流温度曲线，从而防止由于过热引起的光致抗蚀剂的劣化。

公开(公告)号：US08866293B2

公开(公告)日：2014-10-21

申请号：US13167086

申请日：2011-06-23

申请人： Yi-Hung Lin ,  Meng-Tsung Lee ,  Sui-An Kao ,  Yi-Hsin Chen ,  Feng-Lung Chien

发明人： Yi-Hung Lin ,  Meng-Tsung Lee ,  Sui-An Kao ,  Yi-Hsin Chen ,  Feng-Lung Chien

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L24/11 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/039 ,  H01L2224/03901 ,  H01L2224/03903 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/0556 ,  H01L2224/05564 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/116 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0132 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2224/0347 ,  H01L2224/1161 ,  H01L2224/05552

摘要： A semiconductor structure includes a semiconductor chip having at least an electrode pad, a first metal layer formed on the electrode pad, a second metal layer completely formed on and in contact with the first metal layer, and a conductive pillar disposed on the second metal layer, where a material of the first metal layer is different from a material of the second metal layer, the first metal layer has a first distribution-projected area larger than a second distribution projected-area of the conductive pillar, and the second metal layer has a third distribution-projected area that is the same as the second distribution-projected area of the conductive pillar.

摘要翻译： 半导体结构包括具有至少电极焊盘，形成在电极焊盘上的第一金属层，完全形成在第一金属层上并与第一金属层接触的第二金属层的半导体芯片和设置在第二金属层上的导电柱 其中，所述第一金属层的材料与所述第二金属层的材料不同，所述第一金属层具有大于所述导电柱的第二分布投影面积的第一分布投影面积，并且所述第二金属层具有 与导电柱的第二分布投影面积相同的第三分布投影面积。