公开(公告)号：US20200285523A1

公开(公告)日：2020-09-10

申请号：US16878861

申请日：2020-05-20

申请人： Francesc Guim Bernat ,  Kshitij Arun Doshi ,  Bassam N. Coury ,  Suraj Prabhakran ,  Timothy Verrall

发明人： Francesc Guim Bernat ,  Kshitij Arun Doshi ,  Bassam N. Coury ,  Suraj Prabhakran ,  Timothy Verrall

IPC分类号： G06F9/50 ,  G06F9/48

摘要： Systems and methods may be used to determine where to run a service based on workload-based conditions or system-level conditions. An example method may include determining whether power available to a resource of a compute device satisfies a target power, for example to satisfy a target performance for a workload. When the power available is insufficient, an additional resource may be provided, for example on a remote device from the compute device. The additional resource may be used as a replacement for the resource of the compute device or to augment the resource of the compute device.

公开(公告)号：US07162560B2

公开(公告)日：2007-01-09

申请号：US10751250

申请日：2003-12-31

申请人： Billy K. Taylor ,  Mohan J. Kumar ,  Wilson E. Smoak ,  David J. O'Shea ,  Bassam N. Coury ,  Priscilla Lam ,  Tom Slaight

发明人： Billy K. Taylor ,  Mohan J. Kumar ,  Wilson E. Smoak ,  David J. O'Shea ,  Bassam N. Coury ,  Priscilla Lam ,  Tom Slaight

IPC分类号： G06F13/24 ,  G06F15/00

CPC分类号： G06F15/177 ,  G06F1/24 ,  G06F9/45533

摘要： A system that may optionally be partitioned into multiple domains is disclosed. Each domain is capable of independently powering on, executing a firmware program, and loading an operating system, including a legacy operating system, as well as running an application program that is distinct from programs running on another domain. Interrupts, including boot interrupts, reset handlers, and inter-chassis communications are initialized differently, depending on whether the system is to be partitioned or not. The cost of redundant hardware and/or firmware is substantially avoided, yet the system fully supports multiple domains.

摘要翻译： 公开了可选地被划分成多个域的系统。 每个域都能够独立地加电，执行固件程序，以及加载包括旧版操作系统在内的操作系统，以及运行与在其他域上运行的程序不同的应用程序。 中断，包括引导中断，复位处理程序和机架间通信根据系统是否要进行分区，进行不同的初始化。 基本上避免了冗余硬件和/或固件的成本，但是系统完全支持多个域。

公开(公告)号：US10331614B2

公开(公告)日：2019-06-25

申请号：US15025988

申请日：2013-11-27

申请人： INTEL CORPORATION ,  Dimitrios Ziakas ,  Bassam N. Coury ,  Mohan J. Kumar ,  Murugasamy K. Nachimuthu ,  Thi Dang ,  Russell J. Wunderlich

发明人： Dimitrios Ziakas ,  Bassam N. Coury ,  Mohan J. Kumar ,  Murugasamy K. Nachimuthu ,  Thi Dang ,  Russell J. Wunderlich

IPC分类号： G06F11/00 ,  G06F15/78 ,  G06F11/10 ,  G06F11/34 ,  G06F11/16

摘要： Systems and methods of implementing server architectures that can facilitate the servicing of memory components in computer systems. The systems and methods employ nonvolatile memory/storage modules that include nonvolatile memory (NVM) that can be used for system memory and mass storage, as well as firmware memory. The respective NVM/storage modules can be received in front or rear-loading bays of the computer systems. The systems and methods further employ single, dual, or quad socket processors, in which each processor is communicably coupled to at least some of the NVM/storage modules disposed in the front or rear-loading bays by one or more memory and/or input/output (I/O) channels. By employing NVM/storage modules that can be received in front or rear-loading bays of computer systems, the systems and methods provide memory component serviceability heretofore unachievable in computer systems implementing conventional server architectures.

公开(公告)号：US09600416B2

公开(公告)日：2017-03-21

申请号：US13997189

申请日：2011-09-30

申请人： Raj K. Ramanujan ,  Rajat Agarwal ,  Kai Cheng ,  Taarinya Polepeddi ,  Camille C. Raad ,  David J. Zimmerman ,  Muthukumar P. Swaminathan ,  Dimitrios Ziakas ,  Mohan J. Kumar ,  Bassam N. Coury ,  Glenn J. Hinton

发明人： Raj K. Ramanujan ,  Rajat Agarwal ,  Kai Cheng ,  Taarinya Polepeddi ,  Camille C. Raad ,  David J. Zimmerman ,  Muthukumar P. Swaminathan ,  Dimitrios Ziakas ,  Mohan J. Kumar ,  Bassam N. Coury ,  Glenn J. Hinton

IPC分类号： G06F13/12 ,  G06F13/38 ,  G06F12/08 ,  G11C11/406 ,  G11C14/00

CPC分类号： G06F12/0811 ,  G06F12/0895 ,  G06F12/0897 ,  G06F2212/2024 ,  G06F2212/205 ,  G11C11/40615 ,  G11C14/009 ,  Y02D10/13

摘要： A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.”

公开(公告)号：US20160183374A1

公开(公告)日：2016-06-23

申请号：US14575775

申请日：2014-12-18

申请人： Mani Prakash ,  Thomas T. Holden ,  Jeffory L. Smalley ,  Ram S. Viswanath ,  Bassam N. Coury ,  Dimitrios Ziakas ,  Chong J. Zhao ,  Jonathan W. Thibado ,  Gregorio R. Murtagian ,  Kuang C. Liu ,  Rajasekaran Swaminathan ,  Zhichao Zhang ,  John M. Lynch ,  David J. Llapitan ,  Sanka Ganesan ,  Xiang Li ,  George Vergis

发明人： Mani Prakash ,  Thomas T. Holden ,  Jeffory L. Smalley ,  Ram S. Viswanath ,  Bassam N. Coury ,  Dimitrios Ziakas ,  Chong J. Zhao ,  Jonathan W. Thibado ,  Gregorio R. Murtagian ,  Kuang C. Liu ,  Rajasekaran Swaminathan ,  Zhichao Zhang ,  John M. Lynch ,  David J. Llapitan ,  Sanka Ganesan ,  Xiang Li ,  George Vergis

IPC分类号： H05K1/18 ,  H01R12/72 ,  H05K1/11 ,  H05K1/02 ,  H05K3/30 ,  H05K3/34

CPC分类号： H05K1/181 ,  H01L23/00 ,  H01L23/498 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01R12/712 ,  H01R12/79 ,  H05K2201/10159 ,  H05K2201/10325 ,  Y02P70/611

摘要： Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.

摘要翻译： 公开了可配置的中央处理单元（CPU）封装基板。 描述了包括处理设备接口的封装衬底。 封装衬底还包括设置在封装衬底上的存储器件电接口。 封装衬底还包括靠近存储器件电接口设置的可移除存储器机械接口。 可移除存储器机械接口是允许在将存储器件附接到封装衬底之后容易地从封装衬底移除存储器件。

公开(公告)号：US20140129767A1

公开(公告)日：2014-05-08

申请号：US13997189

申请日：2011-09-30

申请人： Raj K Ramanujan ,  Rajat Agarwal ,  Kai Cheng ,  Taarinya Polepeddi ,  Camille C. Raad ,  David J. Zimmerman ,  Muthukumar P. Swaminathan ,  Dimitrios Ziakas ,  Mohan J. Kumar ,  Bassam N. Coury ,  Glenn N. Hinton

发明人： Raj K Ramanujan ,  Rajat Agarwal ,  Kai Cheng ,  Taarinya Polepeddi ,  Camille C. Raad ,  David J. Zimmerman ,  Muthukumar P. Swaminathan ,  Dimitrios Ziakas ,  Mohan J. Kumar ,  Bassam N. Coury ,  Glenn N. Hinton

IPC分类号： G06F12/08 ,  G11C14/00 ,  G11C11/406

CPC分类号： G06F12/0811 ,  G06F12/0895 ,  G06F12/0897 ,  G06F2212/2024 ,  G06F2212/205 ,  G11C11/40615 ,  G11C14/009 ,  Y02D10/13

摘要： A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.”

摘要翻译： 描述了用于集成包括计算机系统内的非易失性存储器层的存储器和存储层级的系统和方法。 在一个实施例中，PCMS存储器件被用作层次结构中的一层，有时被称为“远存储器”。更高性能的存储器件例如放置在远存储器之前的DRAM，并用于掩盖某些性能限制 远记忆 这些更高性能的存储器件被称为“接近存储器”。