Process flow for a combined CA and TSV oxide deposition

    公开(公告)号:US10068835B2

    公开(公告)日:2018-09-04

    申请号:US15461538

    申请日:2017-03-17

    Inventor: Christian Klewer

    Abstract: A method of forming a TSV isolation layer and a transistor-to-BEOL isolation layer during a single deposition process and the resulting device are disclosed. Embodiments include providing a gate stack, with source/drain regions at opposite sides thereof, and an STI layer on a silicon substrate; forming a TSV trench, laterally separated from the gate stack, through the STI layer and the silicon substrate; forming an isolation layer on sidewalls and a bottom surface of the TSV trench and over the gate stack, the STI layer, and the silicon substrate; forming a TSV in the TSV trench; forming a dielectric cap over the isolation layer and the TSV; and forming a source/drain contact through the dielectric cap and the isolation layer down to the source/drain contract regions.

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