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    CHIP PACKAGE CARRIER AND FABRICATION METHOD THEREOF
    1.
    发明申请
    CHIP PACKAGE CARRIER AND FABRICATION METHOD THEREOF 有权
    芯片包装机及其制造方法

    公开(公告)号：US20100013068A1

    公开(公告)日：2010-01-21

    申请号：US12208843

    申请日：2008-09-11

    申请人： Han-Pei Huang ,  Chih-Peng Fan

    发明人： Han-Pei Huang ,  Chih-Peng Fan

    IPC分类号： H01L23/495 ,  H01L21/00

    CPC分类号： H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/4334 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/16 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K1/115 ,  H05K1/162 ,  H05K3/4602 ,  H05K2201/09518 ,  H05K2201/09809 ,  H01L2224/0401

    摘要： A chip package carrier is disclosed, which includes a first circuit layer, a second circuit layer, a core layer, a third circuit layer, a first dielectric layer between the first and third circuit layers, a fourth conductive layer including at least a solder ball pad, a second dielectric layer between the second and fourth circuit layers and at least a capacitor device, wherein the core layer has at least a first through-hole; the third circuit layer is disposed above the first circuit layer and includes at least a die pad; the capacitor device is disposed in the first through-hole. The capacitor device herein includes a first pillar electrode covering the wall of the first through-hole, a cylindrical capacitor material disposed in the first pillar electrode and having a first blind hole, and a second pillar electrode disposed in the first blind hole and connected to the die pad.

    摘要翻译： 公开了一种芯片封装载体，其包括第一电路层，第二电路层，芯层，第三电路层，第一和第三电路层之间的第一电介质层，第四导电层，至少包括焊球 垫，第二和第四电路层之间的第二电介质层和至少一个电容器器件，其中芯层至少具有第一通孔; 所述第三电路层设置在所述第一电路层上方，并且至少包括管芯焊盘; 电容器装置设置在第一通孔中。 本发明的电容器件包括覆盖第一通孔的壁的第一柱状电极，设置在第一柱状电极中并具有第一盲孔的圆筒形电容器材料和设置在第一盲孔中的第二柱状电极， 芯片垫。

    Carrier and Method for Fabricating Thereof
    4.
    发明申请
    Carrier and Method for Fabricating Thereof 审中-公开
    载体及其制造方法

    公开(公告)号：US20120255770A1

    公开(公告)日：2012-10-11

    申请号：US13370360

    申请日：2012-02-10

    申请人： Han-Pei Huang ,  Yu-Ying Chao ,  Chih-Hsueh Shih

    发明人： Han-Pei Huang ,  Yu-Ying Chao ,  Chih-Hsueh Shih

    IPC分类号： H05K1/11 ,  B32B37/14 ,  B32B37/10

    CPC分类号： H04R31/00 ,  B81B7/0041 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81C1/00293 ,  H04R19/005 ,  H04R2201/003

    摘要： A method for fabricating a carrier is disclosed, wherein the carrier is applied for a microelectromechanical sensing device. The method includes the steps of: providing a first substrate, wherein the first substrate includes a first metal layer, a first dielectric layer, and a first opening; providing a second substrate, wherein the second substrate includes a second metal layer, a second dielectric layer, and a second opening; providing a reticular element; pressing the first substrate, the reticular element, and the second substrate to form a composite substrate, wherein the first opening and the second opening form a hole, and the reticular element is positioned in the hole; and forming at least one conductive via in the composite substrate.

    摘要翻译： 公开了一种用于制造载体的方法，其中载体被应用于微机电感测装置。 该方法包括以下步骤：提供第一衬底，其中第一衬底包括第一金属层，第一介电层和第一开口; 提供第二基板，其中所述第二基板包括第二金属层，第二介电层和第二开口; 提供网状元素; 按压第一基板，网状元件和第二基板以形成复合基板，其中第一开口和第二开口形成孔，网状元件位于孔中; 以及在所述复合衬底中形成至少一个导电通孔。

    MULTILAYER THREE-DIMENSIONAL CIRCUIT STRUCTURE
    8.
    发明申请
    MULTILAYER THREE-DIMENSIONAL CIRCUIT STRUCTURE 审中-公开
    多层三维电路结构

    公开(公告)号：US20110253435A1

    公开(公告)日：2011-10-20

    申请号：US13166133

    申请日：2011-06-22

    申请人： Han-Pei Huang ,  Cheng-Hung Yu

    发明人： Han-Pei Huang ,  Cheng-Hung Yu

    IPC分类号： H05K1/03 ,  H05K1/11

    CPC分类号： H05K3/4644 ,  B33Y10/00 ,  B33Y80/00 ,  H05K1/0284 ,  H05K3/046 ,  H05K3/06 ,  H05K3/185 ,  H05K3/205 ,  H05K3/386 ,  H05K2201/0236 ,  H05K2201/09118 ,  H05K2203/0108 ,  H05K2203/013 ,  H05K2203/107 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

    摘要： A multilayer three-dimensional circuit structure and a manufacturing method thereof are provided in the present invention. The manufacturing method includes following steps. First, a three-dimensional insulating structure is provided. A first three-dimensional circuit structure is then formed on a surface of the three-dimensional insulating structure. Next, an insulating layer covering the first three-dimensional circuit structure is formed. Thereafter, a second three-dimensional circuit structure is formed on the insulating layer. Subsequently, at least a conductive via penetrating the insulating layer is formed for electrically connecting the second three-dimensional circuit structure and the first three-dimensional circuit structure.

    摘要翻译： 本发明提供了一种多层三维电路结构及其制造方法。 制造方法包括以下步骤。 首先，提供三维绝缘结构。 然后在三维绝缘结构的表面上形成第一三维电路结构。 接下来，形成覆盖第一三维电路结构的绝缘层。 此后，在绝缘层上形成第二三维电路结构。 随后，至少形成了穿过绝缘层的导电通孔，用于电连接第二三维电路结构和第一三维电路结构。

    Multilayer three-dimensional circuit structure and manufacturing method thereof
    9.
    发明授权
    Multilayer three-dimensional circuit structure and manufacturing method thereof 有权
    多层三维电路结构及其制造方法

    公开(公告)号：US07987589B2

    公开(公告)日：2011-08-02

    申请号：US12333014

    申请日：2008-12-11

    申请人： Han-Pei Huang ,  Cheng-Hung Yu

    发明人： Han-Pei Huang ,  Cheng-Hung Yu

    IPC分类号： H05K3/02

    CPC分类号： H05K3/4644 ,  B33Y10/00 ,  B33Y80/00 ,  H05K1/0284 ,  H05K3/046 ,  H05K3/06 ,  H05K3/185 ,  H05K3/205 ,  H05K3/386 ,  H05K2201/0236 ,  H05K2201/09118 ,  H05K2203/0108 ,  H05K2203/013 ,  H05K2203/107 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

    摘要： A multilayer three-dimensional circuit structure and a manufacturing method thereof are provided in the present invention. The manufacturing method includes following steps. First, a three-dimensional insulating structure is provided. A first three-dimensional circuit structure is then formed on a surface of the three-dimensional insulating structure. Next, an insulating layer covering the first three-dimensional circuit structure is formed. Thereafter, a second three-dimensional circuit structure is formed on the insulating layer. Subsequently, at least a conductive via penetrating the insulating layer is formed for electrically connecting the second three-dimensional circuit structure and the first three-dimensional circuit structure.

    摘要翻译： 本发明提供了一种多层三维电路结构及其制造方法。 制造方法包括以下步骤。 首先，提供三维绝缘结构。 然后在三维绝缘结构的表面上形成第一三维电路结构。 接下来，形成覆盖第一三维电路结构的绝缘层。 此后，在绝缘层上形成第二三维电路结构。 随后，至少形成了穿过绝缘层的导电通孔，用于电连接第二三维电路结构和第一三维电路结构。