公开(公告)号：US20050127421A1

公开(公告)日：2005-06-16

申请号：US10502930

申请日：2003-01-16

申请人： Harald Seidl ,  Jorn Lutzen ,  Gerhard Beitel ,  Thomas Hecht ,  Annette Sanger ,  Albert Birner

发明人： Harald Seidl ,  Jorn Lutzen ,  Gerhard Beitel ,  Thomas Hecht ,  Annette Sanger ,  Albert Birner

IPC分类号： H01L21/02 ,  H01L21/28 ,  H01L21/314 ,  H01L21/8242 ,  H01L29/51 ,  H01L27/108

CPC分类号： H01L21/28194 ,  H01L21/02175 ,  H01L21/02282 ,  H01L21/314 ,  H01L27/1085 ,  H01L27/10861 ,  H01L27/10873 ,  H01L28/40 ,  H01L29/517

摘要： A semiconductor module is described which is essentially constructed from a silicon material and has an insulation layer for example in the form of a gate insulation layer or a MOS transistor or in the form of an insulation layer of a memory cell for a dynamic memory module. The insulation layer preferably comprises a dielectric material whose band gap is greater than the band gap of SiO2. To construct the insulation layer, use is made of materials which have a metal-fluorine compound, such as e.g. lithium fluoride. Particularly thin insulation layers are provided by the material described.

摘要翻译： 描述了一种半导体模块，其基本上由硅材料构成，并且具有例如栅极绝缘层或MOS晶体管形式的绝缘层，或以动态存储器模块的存储单元的绝缘层的形式。 绝缘层优选地包括其带隙大于SiO 2带隙的电介质材料。 为了构造绝缘层，使用具有金属 - 氟化合物的材料，例如， 氟化锂。 通过所述材料提供特别薄的绝缘层。

公开(公告)号：US07176514B2

公开(公告)日：2007-02-13

申请号：US10413812

申请日：2003-04-15

申请人： Thomas Hecht ,  Albert Birner ,  Harald Seidl ,  Uwe Schröder ,  Stefan Jakschik ,  Martin Gutsche

发明人： Thomas Hecht ,  Albert Birner ,  Harald Seidl ,  Uwe Schröder ,  Stefan Jakschik ,  Martin Gutsche

IPC分类号： H01L27/108 ,  H01L21/76

CPC分类号： H01L21/02238 ,  C25D11/02 ,  C25D11/32 ,  H01L21/02258 ,  H01L21/31675 ,  H01L21/31687 ,  H01L27/1085

摘要： A method for producing a dielectric layer on a substrate made of a conductive substrate material includes reducing a leakage current that flows through defects of the dielectric layer at least by a self-aligning and self-limiting electrochemical conversion of the conductive substrate material into a nonconductive substrate follow-up material in sections of the substrate that are adjacent to the defects. Also provided is a configuration including a dielectric layer with defects, a substrate made of a conductive substrate material, and reinforcement regions made of the nonconductive substrate follow-up material in sections adjacent to the defects.

摘要翻译： 用于在由导电基板材料制成的基板上制造介电层的方法包括至少通过导电基板材料的自对准和自限制电化学转换为不导电的方式减少流过电介质层的缺陷的漏电流 衬底跟随材料在与缺陷相邻的衬底的部分中。 还提供了包括具有缺陷的电介质层，由导电基板材料制成的基板以及由与该缺陷相邻的部分中的非导电性基板追随材料制成的加强区域的结构。

公开(公告)号：US07157371B2

公开(公告)日：2007-01-02

申请号：US10653599

申请日：2003-09-02

申请人： Thomas Hecht ,  Uwe Schroeder ,  Harald Seidl ,  Martin Gutsche ,  Stefan Jakschik ,  Stephan Kudelka ,  Albert Birner

发明人： Thomas Hecht ,  Uwe Schroeder ,  Harald Seidl ,  Martin Gutsche ,  Stefan Jakschik ,  Stephan Kudelka ,  Albert Birner

IPC分类号： H01L21/44

CPC分类号： H01L27/11502 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/28061 ,  H01L21/31138 ,  H01L21/31604 ,  H01L21/3162 ,  H01L21/76802 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L27/11507 ,  H01L28/57 ,  H01L29/0895 ,  H01L29/4941

摘要： A dielectric barrier layer composed of a metal oxide is applied in thin layers with a thickness of less than 20 nanometers in the course of processing semiconductor devices by sequential gas phase deposition or molecular beam epitaxy in molecular individual layers on differently structured base substrates. The method allows, inter alias, effective conductive diffusion barriers to be formed from a dielectric material, an optimization of the layer thickness of the barrier layer, an increase in the temperature budget for subsequent process steps, and a reduction in the effort for removing the temporary barrier layers.

摘要翻译： 由金属氧化物构成的电介质阻挡层通过在不同结构的基底衬底上的分子单层中的顺序气相沉积或分子束外延处理半导体器件的过程中以小于20纳米的厚度施加。 该方法允许间隔地从电介质材料形成有效的导电扩散阻挡层，优化阻挡层的层厚度，随后的工艺步骤的温度预算的增加以及用于去除 临时阻隔层。

公开(公告)号：US20060127576A1

公开(公告)日：2006-06-15

申请号：US10529412

申请日：2003-09-24

申请人： Thomas Hecht ,  Jorn Lutzen

发明人： Thomas Hecht ,  Jorn Lutzen

IPC分类号： C23C16/00

CPC分类号： C23C16/4412 ,  C23C16/45544 ,  C23C16/45557

摘要： In a process chamber of a process reactor, a sequential gas phase deposition (ALD, atomic layer deposition) of two or more precursors fed in by means of process gases is controlled. The process chamber is connected to an auxiliary chamber for a change of precursor and so the precursor to be removed is rarefied in the process chamber, so that a process duration of the sequential gas phase deposition that is determined by a change of precursor is reduced.

摘要翻译： 在工艺反应器的处理室中，控制通过工艺气体进料的两种或多种前体的顺序气相沉积（ALD，原子层沉积）。 处理室连接到辅助室以改变前体，因此待处理的前体在处理室中被稀释，使得由前体变化确定的连续气相沉积的工艺持续时间减少。

公开(公告)号：US20050158945A1

公开(公告)日：2005-07-21

申请号：US10980069

申请日：2004-11-03

申请人： Albert Birner ,  Matthias Foerster ,  Thomas Hecht ,  Michael Stadtmueller ,  Andreas Orth

发明人： Albert Birner ,  Matthias Foerster ,  Thomas Hecht ,  Michael Stadtmueller ,  Andreas Orth

IPC分类号： H01L21/8239 ,  H01L21/334 ,  H01L21/8229 ,  H01L21/8242 ,  H01L29/94

CPC分类号： H01L29/66181 ,  H01L29/945

摘要： The invention provides a method for fabricating a memory cell, a substrate (101) being provided, a trench-type depression (102) being etched into the substrate (101), a barrier layer (103) being deposited non-conformally in the trench-type depression (102), grain elements (104) being grown on the inner areas of the trench-type depression (102), a dielectric layer (202) being deposited on the surfaces of the grain elements and the inner areas of the trench-type depression, and a conduction layer being deposited on the dielectric layer, the grain elements (104) growing selectively on the inner areas (105) of the trench-type depression (102) in an electrode region (301) forming a lower region of the trench-type depression (102) and an amorphous silicon layer continuing to grow in a collar region (302) forming an upper region of the trench-type depression (102).

摘要翻译： 本发明提供了一种用于制造存储单元的方法，提供了一种衬底（101），蚀刻到衬底（101）中的沟槽型凹陷（102），在沟槽中非保形地沉积的阻挡层（103） 型凹陷（102），在沟槽型凹部（102）的内部区域上生长的晶粒元素（104），沉积在晶粒元素的表面上的介电层（202）和沟槽的内部区域 型凹陷，并且导电层沉积在电介质层上，晶粒元素（104）选择性地生长在形成下部区域的电极区域（301）中的沟槽型凹陷（102）的内部区域（105） 的沟槽型凹陷（102）和在形成沟槽型凹陷（102）的上部区域的凸缘区域（302）中继续生长的非晶硅层。

公开(公告)号：US06693016B2

公开(公告)日：2004-02-17

申请号：US10233690

申请日：2002-09-03

申请人： Martin Gutsche ,  Thomas Hecht ,  Matthias Leonhardt ,  Uwe Schröder ,  Harald Seidl

发明人： Martin Gutsche ,  Thomas Hecht ,  Matthias Leonhardt ,  Uwe Schröder ,  Harald Seidl

IPC分类号： H01L2120

CPC分类号： H01L27/10861

摘要： The novel trench capacitors have a constant or increased capacitance. Materials for a second electrode region and if appropriate a first electrode region include a metallic material, a metal nitride, or the like, and/or a dielectric region is formed with a material with an increased dielectric constant. An insulation region is formed in the upper wall region of the trench after the first electrode region or the second electrode region has been formed, by selective and local oxidation.

摘要翻译： 新颖的沟槽电容器具有恒定或增加的电容。 第二电极区域的材料和适当的第一电极区域包括金属材料，金属氮化物等，和/或介电区域由介电常数增加的材料形成。 通过选择性和局部氧化，在形成第一电极区域或第二电极区域之后，在沟槽的上壁区域中形成绝缘区域。

公开(公告)号：US20060264054A1

公开(公告)日：2006-11-23

申请号：US11100325

申请日：2005-04-06

申请人： Martin Gutsche ,  Thomas Hecht ,  Harald Seidl ,  Uwe Rudolph ,  Barbara Lorenz ,  Elisabeth Weikmann

发明人： Martin Gutsche ,  Thomas Hecht ,  Harald Seidl ,  Uwe Rudolph ,  Barbara Lorenz ,  Elisabeth Weikmann

IPC分类号： H01L21/465

CPC分类号： H01L21/30655 ,  H01L21/743 ,  H01L21/76898

摘要： The present invention relates to a method for etching a trench in a semiconductor substrate. More specifically, the present invention relates to a method for etching deep trenches such as those having aspect ratios of 30 and higher. According to embodiments of the invention, a method for etching a trench in a semiconductor substrate includes a first etch cycle wherein the trench is etched to a first depth. Thereafter, a protective liner is deposited on at least the upper part of the trench's sidewalls. The protective liner includes inorganic material. During at least one second etch cycle, the trench is etched to its final depth.

摘要翻译： 本发明涉及一种用于蚀刻半导体衬底中的沟槽的方法。 更具体地说，本发明涉及一种蚀刻深沟槽的方法，例如具有30或更高的纵横比的那些。 根据本发明的实施例，用于蚀刻半导体衬底中的沟槽的方法包括第一蚀刻循环，其中沟槽被蚀刻到第一深度。 此后，保护性衬垫至少沉积在沟槽侧壁的上部。 保护性衬垫包括无机材料。 在至少一个第二蚀刻周期期间，将沟槽蚀刻到其最终深度。

公开(公告)号：US07087485B2

公开(公告)日：2006-08-08

申请号：US10765052

申请日：2004-01-28

申请人： Harald Seidl ,  Martin Gutsche ,  Thomas Hecht

发明人： Harald Seidl ,  Martin Gutsche ,  Thomas Hecht

IPC分类号： H01L21/8242

CPC分类号： H01L21/3141 ,  H01L21/31116 ,  H01L27/1087

摘要： A method for fabricating patterned ceramic layers on areas of a relief structure, wherein the layers may be arranged essentially perpendicular to a top side of a substrate. In exemplary embodiments, a patterned ceramic layer forms an oxide collar for a trench capacitor. The oxide collar is produced by a trench firstly being filled with a resist in its lower section, and an oxide layer subsequently being produced on the uncovered areas of the substrate with the aid of a low temperature ALD method. By means of anisotropic etching, only those portions of the ceramic layer which are arranged at the perpendicular walls of the trench remain. The resist filling may subsequently be removed, for example, by means of an oxygen plasma.

摘要翻译： 一种用于在浮雕结构的区域上制造图案化陶瓷层的方法，其中所述层可以布置成基本上垂直于衬底的顶侧。 在示例性实施例中，图案化陶瓷层形成用于沟槽电容器的氧化物环。 氧化物套环由首先在其下部填充有抗蚀剂的沟槽产生，随后在低温ALD方法的帮助下在衬底的未覆盖区域上产生氧化物层。 通过各向异性蚀刻，仅保留布置在沟槽的垂直壁处的陶瓷层的那些部分。 可以随后例如通过氧等离子体去除抗蚀剂填充。

公开(公告)号：US06835417B2

公开(公告)日：2004-12-28

申请号：US10375529

申请日：2003-02-27

申请人： Annette Saenger ,  Bernhard Sell ,  Harald Seidl ,  Thomas Hecht ,  Martin Gutsche

发明人： Annette Saenger ,  Bernhard Sell ,  Harald Seidl ,  Thomas Hecht ,  Martin Gutsche

IPC分类号： C23C1600

CPC分类号： C23C16/45527 ,  C23C16/34 ,  C23C16/40 ,  C23C16/42 ,  C23C16/45544 ,  C23C16/46 ,  C23C16/481

摘要： The ALD process chamber has heating radiation sources and the process sequence includes rapid temperature changes on a substrate surface of a substrate arranged in the ALD process chamber. The temperature changes are controlled and the ALD and CVD processes are optimized by in situ temperature steps, for example in order to produce nanolaminates.

摘要翻译： ALD处理室具有加热辐射源，并且工艺顺序包括在布置在ALD处理室中的衬底的衬底表面上的快速温度变化。 控制温度变化，并通过原位温度步骤优化ALD和CVD工艺，例如为了生产纳米级氨基酸。

公开(公告)号：US20050037565A1

公开(公告)日：2005-02-17

申请号：US10765052

申请日：2004-01-28

申请人： Harald Seidl ,  Martin Gutsche ,  Thomas Hecht

发明人： Harald Seidl ,  Martin Gutsche ,  Thomas Hecht

IPC分类号： C23C16/00 ,  H01L21/02 ,  H01L21/31 ,  H01L21/311 ,  H01L21/314 ,  H01L21/70 ,  H01L21/8234 ,  H01L21/8242

CPC分类号： H01L21/3141 ,  H01L21/31116 ,  H01L27/1087

摘要： A method for fabricating patterned ceramic layers on areas of a relief structure, wherein the layers may be arranged essentially perpendicular to a top side of a substrate. In exemplary embodiments, a patterned ceramic layer forms an oxide collar for a trench capacitor. The oxide collar is produced by a trench firstly being filled with a resist in its lower section, and an oxide layer subsequently being produced on the uncovered areas of the substrate with the aid of a low temperature ALD method. By means of anisotropic etching, only those portions of the ceramic layer which are arranged at the perpendicular walls of the trench remain. The resist filling may subsequently be removed, for example, by means of an oxygen plasma.

摘要翻译： 一种用于在浮雕结构的区域上制造图案化陶瓷层的方法，其中所述层可以布置成基本上垂直于衬底的顶侧。 在示例性实施例中，图案化陶瓷层形成用于沟槽电容器的氧化物环。 氧化物套环由首先在其下部填充有抗蚀剂的沟槽产生，随后在低温ALD方法的帮助下在衬底的未覆盖区域上产生氧化物层。 通过各向异性蚀刻，仅保留布置在沟槽的垂直壁处的陶瓷层的那些部分。 可以随后例如通过氧等离子体去除抗蚀剂填充。