公开(公告)号：US06445064B1

公开(公告)日：2002-09-03

申请号：US09906794

申请日：2001-07-18

申请人： Hideki Ishii ,  Kazunari Michii ,  Jun Shibata ,  Moriyoshi Nakashima

发明人： Hideki Ishii ,  Kazunari Michii ,  Jun Shibata ,  Moriyoshi Nakashima

IPC分类号： H01L2302

CPC分类号： H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2225/06551 ,  H01L2225/06568 ,  H01L2225/1011 ,  H01L2225/1029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10161 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device includes a first semiconductor package and a second semiconductor package which is mounted onto the first semiconductor package. The first semiconductor package has lands on an upper surface for mounting the second semiconductor package and lands on the lower surface for external connection, which are used for connection with a mounting substrate. The second semiconductor package has external leads which are connected to the lands for mounting the second semiconductor package.

摘要翻译： 半导体器件包括安装在第一半导体封装上的第一半导体封装和第二半导体封装。 第一半导体封装具有用于安装第二半导体封装的上表面的平台，并且用于与安装基板连接的用于外部连接的下表面。 第二半导体封装具有连接到用于安装第二半导体封装的焊盘的外部引线。

公开(公告)号：US06836007B2

公开(公告)日：2004-12-28

申请号：US10383734

申请日：2003-03-10

申请人： Kazunari Michii ,  Jun Shibata

发明人： Kazunari Michii ,  Jun Shibata

IPC分类号： H01L2352

CPC分类号： H01L24/06 ,  H01L23/3114 ,  H01L23/4951 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package includes an upper substrate having an opening portion, a solder ball for connection between substrates arranged on the lower side of the upper substrate, a lower substrate arranged on the further lower side and having an opening portion, a solder ball for external connection connected on the lower surface of the lower substrate, and a semiconductor chip affixed on each substrate. The semiconductor chip is electrically connected to the solder ball through the opening portion of each substrate. The solder ball for connection between substrates is electrically connected to the solder ball for external connection.

摘要翻译： 半导体封装包括具有开口部分的上基板，用于在布置在上基板的下侧上的基板之间连接的焊球，设置在下侧的下基板和具有开口部分，用于外部连接的焊球 连接在下基板的下表面上，以及固定在每个基板上的半导体芯片。 半导体芯片通过每个基板的开口部分电连接到焊球。 用于衬底之间连接的焊球电连接到用于外部连接的焊球。

公开(公告)号：US07709475B2

公开(公告)日：2010-05-04

申请号：US11596735

申请日：2005-05-19

申请人： Yoshikazu Iwasawa ,  Jun Shibata ,  Tadashi Shimamura ,  Hideki Kurihara ,  Takashi Mita ,  Nobuhiko Kawanishi ,  Takashi Hashihayata ,  Mikako Kawamura ,  Takeshi Sagara ,  Sachie Arai ,  Hiroshi Hirai

发明人： Yoshikazu Iwasawa ,  Jun Shibata ,  Tadashi Shimamura ,  Hideki Kurihara ,  Takashi Mita ,  Nobuhiko Kawanishi ,  Takashi Hashihayata ,  Mikako Kawamura ,  Takeshi Sagara ,  Sachie Arai ,  Hiroshi Hirai

IPC分类号： C07D417/12 ,  A61K31/506 ,  C07D417/14 ,  C07D491/08

CPC分类号： C07D417/14 ,  C07D417/12 ,  C07D491/08

摘要： The present invention relates to a compound represented by Formula [I]: wherein X is O, S, NH or CH2; Y1, Y2, Y3, Y4 and Y5, which may be identical or different, are each CH or N; however, at least one of Y1, Y2, Y3, Y4 and Y5 is N; Z1 and Z2, which may be identical or different, are each CH or N; n is an integer from 1 to 3; R1 is a C3-C8 cycloalkyl group, a C6-C10 aryl group, an aliphatic heterocyclic ring or an aromatic heterocyclic ring, or a bicyclic aliphatic saturated hydrocarbon group; R2 and R3, which may be identical or different, are each a hydrogen atom, a lower alkyl group, a lower alkenyl group, a C3-C8 cycloalkyl group, a C6-C10 aryl group, an aromatic heterocyclic ring, or the like; and R4 is a hydrogen atom, a lower alkyl group, a C3-C6 cycloalkyl group or the like, or a pharmaceutically acceptable salt or ester thereof, and a selective inhibitor against Cdk4 and/or Cdk6 or an anticancer agent containing the compound or a pharmaceutically acceptable salt or ester thereof.

摘要翻译： 本发明涉及由式[I]表示的化合物：其中X是O，S，NH或CH 2; Y1，Y2，Y3，Y4和Y5可以相同或不同，分别为CH或N; 然而，Y 1，Y 2，Y 3，Y 4和Y 5中的至少一个为N; 可以相同或不同的Z 1和Z 2各自为CH或N; n为1〜3的整数， R1是C3-C8环烷基，C6-C10芳基，脂族杂环或芳族杂环，或双环脂族饱和烃基; R2和R3可以相同或不同，分别为氢原子，低级烷基，低级烯基，C3-C8环烷基，C6-C10芳基，芳族杂环等; R4为氢原子，低级烷基，C3-C6环烷基等，或其药学上可接受的盐或酯，以及对Cdk4和/或Cdk6的选择性抑制剂或含有该化合物或 其药学上可接受的盐或酯。

公开(公告)号：US07046960B2

公开(公告)日：2006-05-16

申请号：US10001759

申请日：2001-10-24

申请人： Makoto Takemoto ,  Katsuyuki Kawase ,  Tetsu Takase ,  Jun Shibata

发明人： Makoto Takemoto ,  Katsuyuki Kawase ,  Tetsu Takase ,  Jun Shibata

IPC分类号： H04B7/14

CPC分类号： H04H20/06 ,  H04B1/52 ,  H04B1/525 ,  H04B7/15585 ,  H04H20/67

摘要： While a spectrum waveform of an output signal from a subtracter (207) is visibly monitored, an operator controls a variable phases shifter (208) based upon a second control signal (CL2) so that a shape of a spectrum waveform of an output signal from a subtracter (207) is approximated to a spectrum waveform of a desirable wave to change a phase of a local oscillation frequency signal from a local oscillator (206). As a result, a phase of a duplicated loop signal is changed. Also, the operator controls a variable attenuator (209) based upon a first control signal (CL1) so that a shape of this spectrum waveform is approximated to a spectrum waveform of a desirable wave (20) to change a signal level of the duplicated loop signal.

摘要翻译： 当可见地监视来自减法器（207）的输出信号的频谱波形时，操作员基于第二控制信号（CL 2）控制可变相移器（208），使得输出信号的频谱波形的形状 近似于从本地振荡器（206）改变本地振荡频率信号的相位的期望波的频谱波形。 结果，改变了重复的环路信号的相位。 另外，操作员根据第一控制信号（CL 1）控制可变衰减器（209），使得该频谱波形的形状近似于期望波（20）的频谱波形，以改变复制的信号的信号电平 回路信号。

公开(公告)号：US06545365B2

公开(公告)日：2003-04-08

申请号：US09781237

申请日：2001-02-13

申请人： Takashi Kondo ,  Koji Bando ,  Jun Shibata ,  Kazuko Narutaki

发明人： Takashi Kondo ,  Koji Bando ,  Jun Shibata ,  Kazuko Narutaki

IPC分类号： H01L2348

CPC分类号： H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

摘要： A resin-sealed chip stack type semiconductor device comprises a substrate placed on many balls, a bottom chip to which wires are connected, a top chip to which wires are connected and mounted above the bottom chip, a non-conductive bonding layer which functions to bond and fix the two chips to each other, and a sealing resin which covers and protects all the components mounted on the substrate. The non-conductive bonding layer is provided by die bonding in such a manner that is at least covers the portion of the bottom chip where the corresponding wires are connected and does not allow generation of a gap between the two chips.

摘要翻译： 一种树脂密封芯片堆叠型半导体器件，包括放置在许多球上的衬底，连接有导线的底部芯片，连接并且安装在底部芯片上方的导线的顶部芯片，非导电结合层，其功能于 将两个芯片彼此粘合并固定，以及密封树脂，其覆盖并保护安装在基板上的所有部件。 非导电结合层通过芯片接合以至少覆盖底部芯片的相应导线连接部分并且不允许在两个芯片之间产生间隙的方式提供。

公开(公告)号：US5834340A

公开(公告)日：1998-11-10

申请号：US977666

申请日：1997-11-24

申请人： Akiyoshi Sawai ,  Haruo Shimamoto ,  Toru Tachikawa ,  Jun Shibata

发明人： Akiyoshi Sawai ,  Haruo Shimamoto ,  Toru Tachikawa ,  Jun Shibata

IPC分类号： H01L21/56 ,  H01L21/58 ,  H01L21/60 ,  H01L21/68 ,  H01L23/12 ,  H01L23/28 ,  H01L23/31 ,  H01L23/367 ,  H01L23/485 ,  H01L23/498 ,  H05K3/30 ,  H01L21/44

CPC分类号： H01L21/568 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L24/28 ,  H01L24/83 ,  H01L2224/11 ,  H01L2224/11003 ,  H01L2224/1147 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/16 ,  H01L2224/17051 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/73203 ,  H01L2224/81207 ,  H01L2224/83102 ,  H01L2224/83104 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2224/92125 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/1579 ,  H01L2924/181 ,  Y10T29/49169

摘要： A pad electrode is formed on a main surface of a semiconductor chip. A passivation film, which covers a surface portion of the pad electrode, is formed on the main surface of the semiconductor chip. An internal connection conductor is formed on a surface portion of the pad electrode. The semiconductor chip is covered with a molding resin which exposes only a top surface of the internal connection conductor. An external connection conductor is formed on a top surface of the internal connection conductor. The external connection conductor has a substantially flat top surface. Thereby, a plastic molded semiconductor package can be easily mounted on a printed board, and can have improved reliability after being joined on the printed board.

公开(公告)号：US5710062A

公开(公告)日：1998-01-20

申请号：US456335

申请日：1995-06-01

申请人： Akiyoshi Sawai ,  Haruo Shimamoto ,  Toru Tachikawa ,  Jun Shibata

发明人： Akiyoshi Sawai ,  Haruo Shimamoto ,  Toru Tachikawa ,  Jun Shibata

IPC分类号： H01L21/56 ,  H01L21/58 ,  H01L21/60 ,  H01L21/68 ,  H01L23/12 ,  H01L23/28 ,  H01L23/31 ,  H01L23/367 ,  H01L23/485 ,  H01L23/498 ,  H05K3/30 ,  H01L21/28

CPC分类号： H01L21/568 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L24/28 ,  H01L24/83 ,  H01L2224/11 ,  H01L2224/11003 ,  H01L2224/1147 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/16 ,  H01L2224/17051 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/73203 ,  H01L2224/81207 ,  H01L2224/83102 ,  H01L2224/83104 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2224/92125 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/1579 ,  H01L2924/181 ,  Y10T29/49169

摘要： A pad electrode is formed on a main surface of a semiconductor chip. A passivation film, which covers a surface portion of the pad electrode, is formed on the main surface of the semiconductor chip. An internal connection conductor is formed on a surface portion of the pad electrode. The semiconductor chip is covered with a molding resin which exposes only a top surface of the internal connection conductor. An external connection conductor is formed on a top surface of the internal connection conductor. The external connection conductor has a substantially flat top surface. Thereby, a plastic molded semiconductor package can be easily mounted on a printed board, and can have improved reliability after being joined on the printed board.

公开(公告)号：US5095200A

公开(公告)日：1992-03-10

申请号：US640278

申请日：1991-01-11

申请人： Kenichi Matsuda ,  Jun Shibata

发明人： Kenichi Matsuda ,  Jun Shibata

IPC分类号： G06E3/00 ,  G11C11/42 ,  H03K3/42 ,  H03K17/795

CPC分类号： H03K17/7955 ,  G06E3/006 ,  G11C11/42 ,  H03K3/42

摘要： An optoelectronic memory, logic, and interconnection device having an optical bistable circuit as an essential element. The optical bistable circuit includes an optical bistable switch which is a light emitting device and a first phototransistor detecting the light emitted from the light emitting device, connected in series, a second phototransistor connected in parallel to the optical bistable switch which does not detect the light emitted from the light emitting device, and a load resistor connected in series to the optical bistable switch. The optoelectronic memory, logic, and interconnection device operates as an optoelectronic memory device turned on and off with the same light source, as an optoelectronic logic device executing exclusive OR operation, or as a light source for reconfigurable optical interconnection.

摘要翻译： 具有光学双稳态电路作为必需元件的光电存储器，逻辑和互连器件。 光学双稳态电路包括光双稳态开关，其是发光器件和第一光电晶体管，其检测从串联连接的发光器件发射的光，并联连接到不检测光的光学双稳态开关的第二光电晶体管 从发光器件发射的负载电阻器和与光学双稳态开关串联连接的负载电阻器。 光电存储器，逻辑器件和互连器件作为光电存储器件工作，作为与执行异或运算的光电逻辑器件相同的光源，或作为用于可重构光互连的光源而导通和截止的光电存储器件。

公开(公告)号：US07582950B2

公开(公告)日：2009-09-01

申请号：US11190011

申请日：2005-07-27

申请人： Kazuhito Matsukawa ,  Tsuyoshi Koga ,  Akio Nishida ,  Yoshiko Higashide ,  Jun Shibata ,  Hiroshi Tobimatsu

发明人： Kazuhito Matsukawa ,  Tsuyoshi Koga ,  Akio Nishida ,  Yoshiko Higashide ,  Jun Shibata ,  Hiroshi Tobimatsu

IPC分类号： H01L29/06

CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： In a semiconductor chip A wherein an element layer 2 having transistors and the like is formed on the front face, and the back face is joined to an underlying member, such as a package substrate, the thickness T is made 100 μm or less, and thereafter, a gettering layer 3 is formed on the back face of the semiconductor chip A. The gettering layer 3 is formed, for example, by polishing the back face of said semiconductor chip A using a polishing machine. Thereby, the yield of devices can be improved in the step for assembling the package.

摘要翻译： 在半导体芯片A中，其中在正面上形成具有晶体管等的元件层2，并且背面与诸如封装基板的底层部件接合，厚度T为100μm以下， 此后，在半导体芯片A的背面上形成吸气层3.吸气层3例如通过使用研磨机对所述半导体芯片A的背面进行研磨而形成。 因此，在组装包装的步骤中可以提高装置的产量。

公开(公告)号：US20060019959A1

公开(公告)日：2006-01-26

申请号：US10532677

申请日：2003-10-27

申请人： Hiroshi Hirai ,  Nobuhiko Kawanishi ,  Masaaki Hirose ,  Tetsuya Sugimoto ,  Kaori Kamijyo ,  Jun Shibata ,  Kouta Masutani

发明人： Hiroshi Hirai ,  Nobuhiko Kawanishi ,  Masaaki Hirose ,  Tetsuya Sugimoto ,  Kaori Kamijyo ,  Jun Shibata ,  Kouta Masutani

IPC分类号： A61K31/498 ,  C07D498/14 ,  C07D491/14

CPC分类号： C07D487/18 ,  A61K31/4995 ,  A61K31/506 ,  A61K31/517 ,  A61K31/5377 ,  A61K31/55 ,  C07D498/18 ,  C07D498/22 ,  C07D515/18 ,  C07D515/22

摘要： A quinoxalinone derivative of the formula (I): or a pharmaceutically acceptable salt or ester thereof, wherein; X is NH, S or the like; Y is O or the like; the partial structure is, for example, the formula: B1, B2, . . . , Bn-1 and Bn, (in which n is 4, 5 or 6) are each independently CH, N or the like; B′1, B′2, . . . , B′n-1 and B′n (in which n is 4, 5 or 6) are each independently hydrogen or the like; and R is hydrogen, lower alkyl or the like.

摘要翻译： 式（I）的喹喔啉酮衍生物或其药学上可接受的盐或酯，其中： X是NH，S等; Y为O等; 该部分结构例如是以下公式：B 1，B 2，...。 。 。 （其中n为4,5或6）各自独立地为CH，N等;其中n为4或5或6。 B'1，B'2，...， 。 。 ，其中n为4,5或6个，各自独立地为氢等;其中n为4或5或6。 和R是氢，低级烷基等。