公开(公告)号：US06836007B2

公开(公告)日：2004-12-28

申请号：US10383734

申请日：2003-03-10

申请人： Kazunari Michii ,  Jun Shibata

发明人： Kazunari Michii ,  Jun Shibata

IPC分类号： H01L2352

CPC分类号： H01L24/06 ,  H01L23/3114 ,  H01L23/4951 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package includes an upper substrate having an opening portion, a solder ball for connection between substrates arranged on the lower side of the upper substrate, a lower substrate arranged on the further lower side and having an opening portion, a solder ball for external connection connected on the lower surface of the lower substrate, and a semiconductor chip affixed on each substrate. The semiconductor chip is electrically connected to the solder ball through the opening portion of each substrate. The solder ball for connection between substrates is electrically connected to the solder ball for external connection.

摘要翻译： 半导体封装包括具有开口部分的上基板，用于在布置在上基板的下侧上的基板之间连接的焊球，设置在下侧的下基板和具有开口部分，用于外部连接的焊球 连接在下基板的下表面上，以及固定在每个基板上的半导体芯片。 半导体芯片通过每个基板的开口部分电连接到焊球。 用于衬底之间连接的焊球电连接到用于外部连接的焊球。

公开(公告)号：US06445064B1

公开(公告)日：2002-09-03

申请号：US09906794

申请日：2001-07-18

申请人： Hideki Ishii ,  Kazunari Michii ,  Jun Shibata ,  Moriyoshi Nakashima

发明人： Hideki Ishii ,  Kazunari Michii ,  Jun Shibata ,  Moriyoshi Nakashima

IPC分类号： H01L2302

CPC分类号： H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2225/06551 ,  H01L2225/06568 ,  H01L2225/1011 ,  H01L2225/1029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10161 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device includes a first semiconductor package and a second semiconductor package which is mounted onto the first semiconductor package. The first semiconductor package has lands on an upper surface for mounting the second semiconductor package and lands on the lower surface for external connection, which are used for connection with a mounting substrate. The second semiconductor package has external leads which are connected to the lands for mounting the second semiconductor package.

摘要翻译： 半导体器件包括安装在第一半导体封装上的第一半导体封装和第二半导体封装。 第一半导体封装具有用于安装第二半导体封装的上表面的平台，并且用于与安装基板连接的用于外部连接的下表面。 第二半导体封装具有连接到用于安装第二半导体封装的焊盘的外部引线。

公开(公告)号：US20060240596A1

公开(公告)日：2006-10-26

申请号：US11473081

申请日：2006-06-23

申请人： Kazunari Michii ,  Naoyuki Shinonaga ,  Shinji Semba

发明人： Kazunari Michii ,  Naoyuki Shinonaga ,  Shinji Semba

IPC分类号： H01L21/00 ,  H01L21/44

CPC分类号： H01L21/561 ,  H01L21/56 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A plurality of semiconductor chips is mounted on a surface of a substrate to be used for manufacturing semiconductor devices. The semiconductor chips are collectively sealed with resin, thereby forming resin-sealed sections. A plurality of solder balls are formed on the back surface of the substrate such that an interval A between the corresponding solder balls of adjacent semiconductor chips becomes “n” times (“n” is an integer greater than 1) an interval B between the solder balls on the semiconductor chip. After the semiconductor chips have been subjected to an electrical test, the resin-sealed sections and the substrate are sliced, thus breaking the semiconductor chips into pieces.

摘要翻译： 多个半导体芯片安装在用于制造半导体器件的基板的表面上。 半导体芯片被树脂共同密封，从而形成树脂密封部。 在基板的背面形成有多个焊球，使得相邻的半导体芯片的相应的焊锡球之间的间隔A成为“n”倍（“n”为大于1的整数）焊料间的间隔B 半导体芯片上的球。 在半导体芯片进行电气测试之后，将树脂密封部分和基板切片，从而将半导体芯片分解成块。

公开(公告)号：US06670701B2

公开(公告)日：2003-12-30

申请号：US10000031

申请日：2001-12-04

申请人： Tetsuya Matsuura ,  Yasushi Kasatani ,  Kazunari Michii ,  Hajime Maeda

发明人： Tetsuya Matsuura ,  Yasushi Kasatani ,  Kazunari Michii ,  Hajime Maeda

IPC分类号： H01L2302

CPC分类号： H05K1/141 ,  H01L25/105 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/15311 ,  H05K1/144 ,  H05K1/145 ,  H05K1/182 ,  H05K1/183 ,  H05K3/3436 ,  H05K2201/045 ,  H05K2201/049 ,  H05K2201/09036 ,  H05K2201/10303 ,  H05K2201/10378 ,  H05K2201/10386 ,  H05K2201/10515 ,  H05K2201/10689 ,  H05K2203/1572

摘要： A semiconductor module achieving higher density of the semiconductor module itself as well as of being disposed in an area-efficient manner relative to another electronic component, such as a mother board and the like. The semiconductor module includes a mounting substrate having, on an underside, a solder ball for connecting to an interconnection of a mother board and semiconductor packages mounted in multiple layers on the top side of the mounting substrate and connected to electrodes on the mounting substrate.

摘要翻译： 实现半导体模块本身的更高密度以及相对于诸如母板等的其他电子部件以区域有效的方式设置的半导体模块。 该半导体模块包括安装基板，其在下侧具有用于连接到母板和安装在安装基板的顶侧上的多层的半导体封装的互连的焊球，并连接到安装基板上的电极。

公开(公告)号：US06518652B2

公开(公告)日：2003-02-11

申请号：US09808151

申请日：2001-03-15

申请人： Yasuki Takata ,  Hiroshi Horibe ,  Kazunari Michii

发明人： Yasuki Takata ,  Hiroshi Horibe ,  Kazunari Michii

IPC分类号： H01L23495

CPC分类号： H01L23/4951 ,  H01L23/49503 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05647 ,  H01L2224/06136 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48647 ,  H01L2224/48747 ,  H01L2224/48847 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85447 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package includes a semiconductor chip, a die pad, an adhesive, metal wires, LOC inner leads, and standard inner leads sealed within a sealing resin. The LOC inner leads and the standard inner leads are arranged in the same plane and both are arranged along one side of the semiconductor chip. Clearance between the inner leads and the die pad larger than the total thickness of the semiconductor chip and the bonding material. Thus, a semiconductor chip having electrode pads broadly distributed can be employed and the section modulus of the semiconductor package can be increased.

摘要翻译： 半导体封装包括半导体芯片，芯片焊盘，粘合剂，金属线，LOC内引线和密封在密封树脂内的标准内引线。 LOC内引线和标准内引线布置在同一平面中，并且都沿着半导体芯片的一侧布置。 内引线和芯片焊盘之间的间隙大于半导体芯片和接合材料的总厚度。 因此，可以采用具有广泛分布的电极焊盘的半导体芯片，并且可以增加半导体封装的截面模数。

公开(公告)号：US5373188A

公开(公告)日：1994-12-13

申请号：US3422

申请日：1993-01-12

申请人： Kazunari Michii ,  Koichi Nakagawa

发明人： Kazunari Michii ,  Koichi Nakagawa

IPC分类号： H01L21/56 ,  H01L21/60 ,  H01L23/28 ,  H01L23/495 ,  H01L23/50 ,  H01L23/538 ,  H01L23/48 ,  H01L29/44 ,  H01L29/52 ,  H01L29/60

CPC分类号： H01L24/06 ,  H01L23/4951 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/32 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/06136 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/82181 ,  H01L2224/85181 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/30107

摘要： A resin-molded multi-chip package semiconductor device includes a lead frame having a plurality of leads including crossing leads that extend over an obverse or a reverse side of one semiconductor element separated from electrical contact with the element by an interposed insulating material. The electrodes of one element and of another element are electrically connected in common to the crossing lead by bonding wires. The device may comprise a TAB tape having leads on an insulating tape, electrically connecting the electrodes of the neighboring elements together. The TAB tape may include crossing leads that cross another TAB lead.

摘要翻译： 树脂模制的多芯片封装半导体器件包括引线框架，该引线框架具有多个引线，引线包括跨越一个半导体元件的正面或反面的交叉引线，该半导体元件通过插入的绝缘材料与元件电接触而分离。 一个元件的电极和另一个元件的电极通过接合线电连接到交叉引线。 该装置可以包括在绝缘带上具有引线的TAB带，将相邻元件的电极电连接在一起。 TAB带可以包括穿过另一TAB引线的交叉引线。

公开(公告)号：US06798056B2

公开(公告)日：2004-09-28

申请号：US10231148

申请日：2002-08-30

申请人： Tetsuya Matsuura ,  Yasushi Kasatani ,  Kazunari Michii

发明人： Tetsuya Matsuura ,  Yasushi Kasatani ,  Kazunari Michii

IPC分类号： H01L2302

CPC分类号： H05K1/181 ,  H01L25/105 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/0002 ,  H05K7/026 ,  H05K2201/10515 ,  H05K2201/10689 ,  Y02P70/611 ,  H01L2924/00

摘要： A semiconductor module includes a substrate having a pad electrode on a surface, a lower layer semiconductor package mounted on the substrate, and an upper layer semiconductor package mounted on the substrate while arranged in a position substantially overlying the former. The pad electrodes connected to the leads of these semiconductor packages are arranged alternately. The lead has a dambar residual portion. An inner surface of a lead downward portion of the upper layer semiconductor package is positioned outside an outer surface of a lead downward portion of the lower layer semiconductor package.

摘要翻译： 半导体模块包括：表面上具有焊盘电极的基板，安装在基板上的下层半导体封装，以及安装在基板上的上层半导体封装，同时布置在基本上覆盖前者的位置。 连接到这些半导体封装的引线的焊盘电极交替布置。 铅带有残渣部分。 上层半导体封装的引线向下部分的内表面位于下层半导体封装的引线向下部分的外表面的外侧。

公开(公告)号：US06614101B2

公开(公告)日：2003-09-02

申请号：US09579268

申请日：2000-05-26

申请人： Kazuyuki Misumi ,  Kazunari Michii ,  Manabu Horita

发明人： Kazuyuki Misumi ,  Kazunari Michii ,  Manabu Horita

IPC分类号： H01L23495

CPC分类号： H01L24/06 ,  H01L23/49503 ,  H01L23/49551 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/06136 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48624 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A plastic packaged semiconductor device is constructed by sealing, with a sealing plastic, a semiconductor chip which has an electrode pad arranged in a central portion of an upper surface, a die pad to which the semiconductor chip is die-bonded, bonding wires which are connected to the electrode pad, and inner leads which are arranged in close vicinity of the die pad and have tip portions having upper flat surfaces which are positioned at a level equal to or higher than the upper surface of the semiconductor chip and to which the bonding wires are connected. Accordingly, the small thin plastic packaged semiconductor device in which the bonding wires do never come into contact with the edge of the semiconductor chip can be achieved.

摘要翻译： 塑料封装半导体器件通过密封塑料制成，半导体芯片具有布置在上表面的中心部分的电极焊盘，半导体芯片被芯片接合的芯片焊盘， 连接到电极焊盘和布置在芯片焊盘附近的内部引线，并且具有顶部部分，其顶部部分具有位于等于或高于半导体芯片的上表面的电平的上部平坦表面， 电线连接。 因此，可以实现其中接合线不会与半导体芯片的边缘接触的小型薄塑料封装半导体器件。

公开(公告)号：US06583511B2

公开(公告)日：2003-06-24

申请号：US09903629

申请日：2001-07-13

申请人： Kazunari Michii ,  Tatsuhiko Akiyama

发明人： Kazunari Michii ,  Tatsuhiko Akiyama

IPC分类号： H01L2348

CPC分类号： H01L24/85 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48599 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48664 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/78703 ,  H01L2224/85148 ,  H01L2224/85205 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85464 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10161 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/20753 ,  H01L2224/48227 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012

摘要： A laminated semiconductor chip assembly fabricated by fixing back surfaces of first and second semiconductor chips, respectively having principal surfaces and back surfaces, to each other. Each of the principal surfaces of the laminated semiconductor chip assembly is fixed to a corresponding surface of a lead frame. A standing linear portion of a metallic wire on a ball bond side is pulled parallel to a side surface of the semiconductor chip in its thickness direction and a side surface of the inner lead in its thickness direction, and subjected to wire bonding. The formed semiconductor chip assembly is covered by a sealing resin so that an outer lead protrudes from the sealing resin. Thus, the semiconductor device can be made thin, cost can be reduced, and quality can be improved to increase capacities of electronic equipment.

摘要翻译： 通过将分别具有主表面和背面的第一和第二半导体芯片的背面相互固定而制成的层叠半导体芯片组件。 层叠半导体芯片组件的每个主表面固定到引线框架的相应表面上。 平行于半导体芯片的厚度方向的侧面和内部引线的厚度方向的侧面平行于金属线的球形接合侧的直立部分进行引线接合。 形成的半导体芯片组件被密封树脂​​覆盖，使得外部引线从密封树脂突出。 因此，可以使半导体器件变薄，可以降低成本，并且可以提高质量以增加电子设备的容量。

公开(公告)号：US5424577A

公开(公告)日：1995-06-13

申请号：US219940

申请日：1994-03-30

申请人： Yasuhito Suzuki ,  Kazunari Michii

发明人： Yasuhito Suzuki ,  Kazunari Michii

IPC分类号： H01L23/28 ,  H01L21/56 ,  H01L23/495 ,  H01L23/50 ,  H01L23/48

CPC分类号： H01L23/49537 ,  H01L21/565 ,  H01L23/49548 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/01078 ,  H01L2924/01079

摘要： A lead frame for semiconductor devices which does not require tie bar cutting in the manufacture of semiconductor devices includes a base lead frame having no tie bars and a dummy lead frame having dummy leads filling gaps between outer lead portions of the leads when the dummy lead frame is mounted on the base lead frame. Instead of tie bars, the dummy leads reinforce the leads and also stop molten sealing resin from flowing into the gaps between the outer lead portions during resin molding.

摘要翻译： 在半导体器件的制造中不需要连接条切割的半导体器件的引线框架包括：没有连接条的基底引线框架和具有虚拟引线的虚拟引线框架，当引线框架的伪引线框架 安装在基底引线框架上。 代替连杆，在树脂成形时，虚拟引线加强引线并且还阻止熔融密封树脂流入外部引线部分之间的间隙。