公开(公告)号：US07788076B2

公开(公告)日：2010-08-31

申请号：US11076212

申请日：2005-03-08

申请人： Hideki Iwaki ,  Tetsuyoshi Ogura ,  Naoki Komatsu ,  Takeshi Nakayama ,  Tomohiro Kinoshita

发明人： Hideki Iwaki ,  Tetsuyoshi Ogura ,  Naoki Komatsu ,  Takeshi Nakayama ,  Tomohiro Kinoshita

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： An interference analysis device can be provided, which analyzes interference between wirings of a circuit board with reduced load and for a short time period. The interference analysis device according to the present invention includes: a design data input part for inputting design data of the circuit board; a noise characteristics setting part that sets data representing electrical characteristics of noise for a wiring of the circuit board; a limit value setting part that sets an allowable limit value of noise received by a wiring; a selection part that selects a wiring group to be analyzed based on the noise characteristics data and the allowable limit value; an interference analysis part that calculates, concerning the selected wiring group, an amount of interference from a wiring giving the interference to a wiring receiving the interference; and a received noise level calculation part that calculates a noise level that the wiring receiving the interference will receive.

摘要翻译： 可以提供干扰分析装置，其分析电路板的布线之间的负载和短时间内的干扰。 根据本发明的干扰分析装置包括：设计数据输入部分，用于输入电路板的设计数据; 噪声特性设定部，其设定表示所述电路基板的布线的噪声的电特性的数据; 极限值设定部，其设定由布线接收到的噪声的允许限制值; 选择部，其基于所述噪声特性数据和所述容许极限值来选择要分析的布线组; 干扰分析部，其对与所述接线组相关的干扰分析部，计算与所述干扰对应的布线的干扰量的干扰量; 以及接收噪声电平计算部，其计算接收到干扰的接线的噪声电平。

公开(公告)号：US20050197817A1

公开(公告)日：2005-09-08

申请号：US11076212

申请日：2005-03-08

申请人： Hideki Iwaki ,  Tetsuyoshi Ogura ,  Naoki Komatsu ,  Takeshi Nakayama ,  Tomohiro Kinoshita

发明人： Hideki Iwaki ,  Tetsuyoshi Ogura ,  Naoki Komatsu ,  Takeshi Nakayama ,  Tomohiro Kinoshita

IPC分类号： G01R31/28 ,  G06F17/50 ,  H01L21/82

CPC分类号： G06F17/5036

摘要： An interference analysis device can be provided, which analyzes interference between wirings of a circuit board with reduced load and for a short time period. The interference analysis device according to the present invention includes: a design data input part for inputting design data of the circuit board; a noise characteristics setting part that sets data representing electrical characteristics of noise for a wiring of the circuit board; a limit value setting part that sets an allowable limit value of noise received by a wiring; a selection part that selects a wiring group to be analyzed based on the noise characteristics data and the allowable limit value; an interference analysis part that calculates, concerning the selected wiring group, an amount of interference from a wiring giving the interference to a wiring receiving the interference; and a received noise level calculation part that calculates a noise level that the wiring receiving the interference will receive.

摘要翻译： 可以提供干扰分析装置，其分析电路板的布线之间的负载和短时间内的干扰。 根据本发明的干扰分析装置包括：设计数据输入部分，用于输入电路板的设计数据; 噪声特性设定部，其设定表示所述电路基板的布线的噪声的电特性的数据; 极限值设定部，其设定由布线接收到的噪声的允许限制值; 选择部，其基于所述噪声特性数据和所述容许极限值来选择要分析的布线组; 干扰分析部，其对与所述接线组相关的干扰分析部，计算与所述干扰对应的布线的干扰量的干扰量; 以及接收噪声电平计算部，其计算接收到干扰的接线的噪声电平。

公开(公告)号：US20090019403A1

公开(公告)日：2009-01-15

申请号：US11911609

申请日：2006-04-14

申请人： Hideki Iwaki ,  Naoki Komatsu ,  Tetsuyoshi Ogura ,  Toru Yamada

发明人： Hideki Iwaki ,  Naoki Komatsu ,  Tetsuyoshi Ogura ,  Toru Yamada

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  H05K1/0216 ,  H05K3/0005

摘要： An interference analysis device that analyzes interference includes an input unit 2 that inputs design data, a selection unit 3 that selects an analysis region, a division unit 5 that divides a wire into segments, a calculation unit 6 that calculates a circuit matrix regarding a coupled line, and an analysis unit 7 that obtains a degree of electromagnetic interference, wherein the calculation unit 6 calculates a circuit matrix of the coupled line, using a parameter set obtained by adding an asymmetry parameter to RLGC parameters of a transmission line in the coupled line. Thus, a method for analyzing an interference of circuit wiring can be provided, which is capable of shortening a processing time substantially while maintaining high precision.

摘要翻译： 分析干扰的干扰分析装置包括：输入设计数据的输入单元2，选择分析区域的选择单元3;将线分割成分段的分割单元5;计算单元6， 线路和获得电磁干扰程度的分析单元7，其中计算单元6使用通过将耦合线路中的传输线路的RLGC参数相加不对称参数获得的参数集来计算耦合线路的电路矩阵 。 因此，可以提供用于分析电路布线的干扰的方法，其能够在保持高精度的同时基本上缩短处理时间。

公开(公告)号：US07814445B2

公开(公告)日：2010-10-12

申请号：US11911609

申请日：2006-04-14

申请人： Hideki Iwaki ,  Naoki Komatsu ,  Tetsuyoshi Ogura ,  Toru Yamada

发明人： Hideki Iwaki ,  Naoki Komatsu ,  Tetsuyoshi Ogura ,  Toru Yamada

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  H05K1/0216 ,  H05K3/0005

摘要： An interference analysis device that analyzes interference includes an input unit that inputs design data, a selection unit that selects an analysis region, a division unit that divides a wire into segments, a calculation unit that calculates a circuit matrix regarding a coupled line, and an analysis unit that obtains a degree of electromagnetic interference, wherein the calculation unit calculates a circuit matrix of the coupled line, using a parameter set obtained by adding an asymmetry parameter to RLGC parameters of a transmission line in the coupled line. Thus, a method for analyzing an interference of circuit wiring can be provided, which is capable of shortening a processing time substantially while maintaining high precision.

摘要翻译： 分析干扰的干扰分析装置包括：输入设备数据的输入单元，选择分析区域的选择单元，将线分割成分段的分割单元;计算与耦合线路有关的电路矩阵的计算单元;以及 分析单元，其中所述计算单元使用通过将耦合线中的传输线的RLGC参数加上不对称参数而获得的参数集来计算所述耦合线路的电路矩阵。 因此，可以提供用于分析电路布线的干扰的方法，其能够在保持高精度的同时基本上缩短处理时间。

公开(公告)号：US06392164B1

公开(公告)日：2002-05-21

申请号：US09417662

申请日：1999-10-14

申请人： Hideki Iwaki ,  Yutaka Taguchi ,  Tetsuyoshi Ogura

发明人： Hideki Iwaki ,  Yutaka Taguchi ,  Tetsuyoshi Ogura

IPC分类号： H05K111

CPC分类号： H05K1/0251 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/024 ,  H05K1/0298 ,  H05K1/116 ,  H05K2201/0715 ,  H05K2201/09454 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09781 ,  H05K2201/09881 ,  H01L2924/00

摘要： An insulator is provided between interconnect layers oppositely placed. The interconnect layers are connected between by connection members provided through the insulator. The connection members at one and the other ends are connected between in their center positions. A shield layer is provided spaced from the intermediate connection layer generally on a same plane as the intermediate connection layer. The interconnect layers where considered generally as a circular cylinder have a diameter m, and the intermediate connection layer where considered generally as circular has a diameter r, r

摘要翻译： 在相互布置的互连层之间设置绝缘体。 互连层通过通过绝缘体提供的连接构件连接在一起。 连接构件在一端和另一端连接在它们的中心位置之间。 屏蔽层设置成与中间连接层间隔开，通常在与中间连接层相同的平面上。 通常被认为是圆柱体的互连层具有直径m，并且被认为通常为圆形的中间连接层具有直径r，r

公开(公告)号：US06885788B2

公开(公告)日：2005-04-26

申请号：US10609494

申请日：2003-06-20

申请人： Hideki Iwaki ,  Yutaka Taguchi ,  Tetsuyoshi Ogura ,  Yasuhiro Sugaya ,  Toshiyuki Asahi ,  Tousaku Nishiyama ,  Yoshinobu Idogawa

发明人： Hideki Iwaki ,  Yutaka Taguchi ,  Tetsuyoshi Ogura ,  Yasuhiro Sugaya ,  Toshiyuki Asahi ,  Tousaku Nishiyama ,  Yoshinobu Idogawa

IPC分类号： H05K3/46 ,  G02B6/43 ,  H05K1/02 ,  H05K1/18 ,  G02B6/10 ,  G02B6/12 ,  G02B6/26 ,  G02B6/42

CPC分类号： G02B6/43 ,  H05K1/0274 ,  H05K1/185

摘要： A light reception/emission device built-in module with optical and electrical wiring combined therein includes: an optical waveguide layer including a core portion and a cladding portion; first and second wiring patterns formed on a main surface of the optical waveguide layer; a light reception device disposed inside the optical waveguide layer, the light reception device being optically connected with the core portion of the optical waveguide layer and being electrically connected with the first wiring pattern; and a light emission device disposed inside the optical waveguide layer, the light emission device being optically connected with the core portion of the optical waveguide layer and being electrically connected with the second wiring pattern. With this configuration, optical coupling between the optical waveguide and the light reception/emission device can be conducted precisely.

摘要翻译： 其中组合有光电布线的光接收/发射装置内置模块包括：包括芯部分和包层部分的光波导层; 形成在光波导层的主表面上的第一和第二布线图案; 光接收装置，其设置在所述光波导层的内部，所述光接收装置与所述光波导层的芯部部分光学连接并与所述第一布线图案电连接; 以及发光装置，其配置在所述光波导层的内部，所述发光装置与所述光波导层的芯部部分光学连接并且与所述第二布线图案电连接。 利用这种结构，可以精确地进行光波导与光接收/发射装置之间的光耦合。

公开(公告)号：US06870264B2

公开(公告)日：2005-03-22

申请号：US09994683

申请日：2001-11-28

申请人： Hideki Iwaki ,  Yutaka Taguchi ,  Tetsuyoshi Ogura

发明人： Hideki Iwaki ,  Yutaka Taguchi ,  Tetsuyoshi Ogura

IPC分类号： H01L23/66 ,  H05K1/00 ,  H05K1/02 ,  H05K1/11 ,  H05K3/46 ,  H01L23/48

CPC分类号： H05K1/0251 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/024 ,  H05K1/0298 ,  H05K1/116 ,  H05K2201/0715 ,  H05K2201/09454 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09781 ,  H05K2201/09881 ,  H01L2924/00

摘要： An insulator is provided between interconnect layers oppositely placed. The interconnect layers are connected between by connection members provided through the insulator. The connection members at one and the other ends are connected between in their center positions. A shield layer is provided spaced from the intermediate connection layer generally on a same plane as the intermediate connection layer. A condition of (R·r)/(2·h)≦L≦(5·R·r)/h is satisfied, provided that a connection distance between the interconnect layers through the connection members and the intermediate connection layer is h, the connection members where considered generally as a circular cylinder have a diameter R, the intermediate connection layer where considered generally as circular has a diameter r, and a spaced distance between the intermediate connection layer and the shield layer is L. Thus, characteristic impedance is stabilized.

摘要翻译： 在相互布置的互连层之间设置绝缘体。 互连层通过通过绝缘体提供的连接构件连接在一起。 连接构件在一端和另一端连接在它们的中心位置之间。 屏蔽层设置成与中间连接层间隔开，通常在与中间连接层相同的平面上。 满足（Rr）/（2.h）<= L <=（5.Rr）/ h的条件，条件是通过连接构件和中间连接层的互连层之间的连接距离为h，连接 通常被认为是圆柱体的构件具有直径R，中间连接层通常被认为是圆形的，具有直径r，并且中间连接层和屏蔽层之间的间隔距离为L.因此，特性阻抗稳定。

公开(公告)号：US08344264B2

公开(公告)日：2013-01-01

申请号：US12489818

申请日：2009-06-23

申请人： Yutaka Kumano ,  Hideki Iwaki ,  Tetsuyoshi Ogura ,  Shingo Komatsu ,  Koichi Hirano

发明人： Yutaka Kumano ,  Hideki Iwaki ,  Tetsuyoshi Ogura ,  Shingo Komatsu ,  Koichi Hirano

IPC分类号： H05K1/11

CPC分类号： H05K3/4046 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/0204 ,  H05K3/4647 ,  H05K2201/10287 ,  H05K2201/10378 ,  H05K2201/10416 ,  H05K2203/0152 ,  Y10T29/49162 ,  H01L2924/00

摘要： A pair of discretionary points on a principal surface of a block are coupled to each other with a metal wire having a length larger than a distance between the pair of discretionary points, liquid resin is applied to the principal surface so as to cover the metal wire and then cured, so that a resin-cured material is formed, and the upper-surface portion of the resin-cured material is removed together with an intermediate portion of the metal wire, and then the block is removed from the resin-cured material.

摘要翻译： 块的主表面上的一对自由点通过长度大于所述一对自由点之间的距离的金属线彼此连接，液体树脂施加到主表面以覆盖金属线 然后固化，从而形成树脂固化材料，树脂固化材料的上表面部分与金属丝的中间部分一起除去，然后将该块从树脂固化材料上除去 。

公开(公告)号：US07385286B2

公开(公告)日：2008-06-10

申请号：US10161719

申请日：2002-06-05

申请人： Hideki Iwaki ,  Tetsuyoshi Ogura ,  Yutaka Taguchi

发明人： Hideki Iwaki ,  Tetsuyoshi Ogura ,  Yutaka Taguchi

IPC分类号： H01L23/34 ,  H01L23/52 ,  H01L23/48 ,  H01L23/495 ,  H01G4/228 ,  H05K1/18

CPC分类号： H05K1/162 ,  H01L23/66 ,  H01L25/0652 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/83192 ,  H01L2924/00013 ,  H01L2924/01025 ,  H01L2924/01037 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15173 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K1/165 ,  H05K1/167 ,  H05K1/185 ,  H05K3/4614 ,  H05K3/4617 ,  H05K3/462 ,  H05K3/4629 ,  H05K2201/09763 ,  H05K2201/10674 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/13099

摘要： At least four terminal electrodes are provided on a surface of multi-layer substrate main body. An electric functional layer is selectively provided at an internal area of said multi-layer substrate placed at a downward position of all terminal electrodes in a substrate thickness direction. A semiconductor device is flip-chip-bonded to the terminal electrodes. Thus, the semiconductor device is electrically connected to the electric functional layer at a short distance. As a result, a reduction in parasitic inductance and an improvement in high frequency characteristic can be accomplished. Generation of height variations between the terminal electrodes can be prevented, and the semiconductor device is stably flip-chip-bonded to the multi-layer substrate.

摘要翻译： 在多层基板主体的表面上设置至少四个端子电极。 选择性地将电功能层设置在位于所有端子电极的向下位置的基板厚度方向上的所述多层基板的内部区域。 将半导体器件倒装芯片接合到端子电极。 因此，半导体器件在短距离处电连接到电功能层。 结果，可以实现寄生电感的降低和高频特性的提高。 可以防止端子电极之间的高度变化的产生，并且半导体器件稳定地倒装芯片地结合到多层基板。

公开(公告)号：US20090174476A1

公开(公告)日：2009-07-09

申请号：US12295480

申请日：2007-03-28

申请人： Naoki Komatsu ,  Hideki Iwaki ,  Toru Yamada

发明人： Naoki Komatsu ,  Hideki Iwaki ,  Toru Yamada

IPC分类号： H03F1/30

CPC分类号： H03F1/26 ,  H01L2223/6627 ,  H01L2924/19032 ,  H01L2924/19051 ,  H03F1/30 ,  H03F3/19 ,  H03F3/245 ,  H05K1/0228 ,  H05K1/0239 ,  H05K2201/10166

摘要： In a noise reduction circuit, a transistor circuit amplifies an input signal and outputs an output signal with supply of power from the DC voltage source via a power supply line circuit. The canceling signal adding circuit acquires and attenuates a part of the output signal, to generate a canceling signal having a phase substantially opposite to a phase of a leakage signal leaking to the power supply line circuit, and having an amplitude substantially the same as an amplitude of the leakage signal.

摘要翻译： 在降噪电路中，晶体管电路对输入信号进行放大，并通过电源线电路输出来自直流电压源的电力的输出信号。 取消信号添加电路获取并衰减输出信号的一部分，以产生具有与泄漏到电源线电路的泄漏信号的相位基本相反的相位并具有与振幅基本相同的振幅的消除信号 的泄漏信号。