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47 条记录 (耗时 0.034 秒)

    Circuit board and method of manufacturing the same
    1.
    发明授权
    Circuit board and method of manufacturing the same 失效
    电路板及其制造方法

    公开(公告)号：US5958600A

    公开(公告)日：1999-09-28

    申请号：US981835

    申请日：1998-01-09

    申请人： Hideo Sotokawa ,  Akira Yabushita ,  Takashi Inoue ,  Hidetaka Shigi ,  Mamoru Ogihara ,  Haruhiko Matsuyama ,  Minoru Tanaka ,  Yasunori Narizuka

    发明人： Hideo Sotokawa ,  Akira Yabushita ,  Takashi Inoue ,  Hidetaka Shigi ,  Mamoru Ogihara ,  Haruhiko Matsuyama ,  Minoru Tanaka ,  Yasunori Narizuka

    IPC分类号： H01L23/498 ,  H01L23/538 ,  B32B15/08 ,  G03C3/00 ,  H05K1/09

    CPC分类号： H01L23/5384 ,  H01L23/49866 ,  H01L23/49894 ,  H01L23/5385 ,  H01L2224/16225 ,  H01L2924/09701 ,  H01L2924/15312 ,  Y10S428/901 ,  Y10T428/24917 ,  Y10T428/31681 ,  Y10T428/31721

    摘要： Disclosed are a highly reliable circuit board and a method of stably manufacturing the circuit board, wherein an insulator made from a specific organic insulating material is provided under a highly stressed conductor for preventing occurrence of cracks in the insulator. In addition, a method of correcting a wiring of a ceramic board is additionally adopted. The circuit board includes a thick film wiring board 1 having a first conductor pattern 2 and a thin film layer laminated on the first conductor pattern 2. The thin film layer includes a first insulator 5 on the first conductor pattern 2; a second insulator 10 on the first insulator 5; a second conductor pattern 8 formed on the first insulator 5 in such a manner as to partially pass through the first insulator 5 and to be electrically connected to the first conductor pattern 2; a wiring pattern 9 for circuit correction formed on the first insulator 5; and a third conductor pattern 11 passing through the first insulator 5 and the second insulator 10 and electrically connected to the second conductor pattern 8.

    摘要翻译： PCT No.PCT / JP96 / 01909 Sec。 371日期1998年1月9日 102（e）1998年1月9日PCT PCT 1996年7月10日PCT公布。 出版物WO97 / 03542 日期1997年1月30日公开是一种高度可靠的电路板和稳定制造电路板的方法，其中由特定有机绝缘材料制成的绝缘体设置在高应力导体下面，以防止在绝缘体中发生裂纹。 此外，另外采用校正陶瓷板的布线的方法。 电路板包括具有层叠在第一导体图案2上的第一导体图案2和薄膜层的厚膜布线板1.薄膜层包括在第一导体图案2上的第一绝缘体5; 第一绝缘体5上的第二绝缘体10; 形成在第一绝缘体5上的部分地通过第一绝缘体5并与第一导体图案2电连接的第二导体图案8; 在第一绝缘体5上形成用于电路校正的布线图案9; 以及穿过第一绝缘体5和第二绝缘体10并电连接到第二导体图案8的第三导体图案11。

    Multilayer wiring board having vent holes and method of making
    2.
    发明授权
    Multilayer wiring board having vent holes and method of making 失效
    具有排气孔的多层接线板及其制造方法

    公开(公告)号：US6124553A

    公开(公告)日：2000-09-26

    申请号：US262270

    申请日：1994-06-20

    申请人： Yasunori Narizuka ,  Naoki Matsushima ,  Hidetaka Shigi ,  Haruhiko Matsuyama

    发明人： Yasunori Narizuka ,  Naoki Matsushima ,  Hidetaka Shigi ,  Haruhiko Matsuyama

    IPC分类号： H05K3/46 ,  H01L23/02 ,  H01L23/12 ,  H01L23/498 ,  H05K1/16

    CPC分类号： H01L23/49838 ,  H01L23/49822 ,  H01L23/49833 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/16152 ,  H01L2924/3025

    摘要： A multilayer wiring system for preventing the generation of fixing failure due to an organic residue, eliminating an increase in the number of processes and reducing an area necessary for bonding of the cap and its fabrication method. The multilayer wiring board includes at least one wiring layer made of a conductor, at least one insulating layer made of an organic matter and a board. The wiring layer and the insulating layer are alternately laminated on the board and a cap is provided for covering the insulating layer and the wiring layer. The wiring layer has a wiring pattern for forming a wiring and a frame pattern for surrounding the wiring pattern. This frame pattern includes vent holes. The insulating layer has a shield structure made of an inorganic matter around the outer peripheral portion thereof and/or in the interior thereof. The shield structure is formed of the frame patterns continuously connected to each other and the cap is joined to an uppermost layer of the shield structure.

    摘要翻译： 一种用于防止由于有机残渣产生固定故障的多层布线系统，消除了工艺数量的增加并减少了盖子接合所需的面积及其制造方法。 多层布线基板包括至少一层由导体制成的布线层，至少一层由有机物制成的绝缘层和基板。 布线层和绝缘层交替地层叠在基板上，并且设置盖以覆盖绝缘层和布线层。 布线层具有用于形成布线的布线图形和用于围绕布线图案的框图案。 该框架图案包括通气孔。 绝缘层具有由外周部分和/或其内部的无机物构成的屏蔽结构。 屏蔽结构由彼此连续连接的框架图案形成，并且盖与屏蔽结构的最上层接合。

    Thin film probe sheet and semiconductor chip inspection system
    7.
    发明申请
    Thin film probe sheet and semiconductor chip inspection system 审中-公开
    薄膜探针片和半导体芯片检测系统

    公开(公告)号：US20060094162A1

    公开(公告)日：2006-05-04

    申请号：US11253575

    申请日：2005-10-20

    申请人： Akira Yabushita ,  Yasunori Narizuka ,  Susumu Kasukabe ,  Terutaka Mori ,  Etsuko Takane ,  Akio Hasebe ,  Kenji Kawakami

    发明人： Akira Yabushita ,  Yasunori Narizuka ,  Susumu Kasukabe ,  Terutaka Mori ,  Etsuko Takane ,  Akio Hasebe ,  Kenji Kawakami

    IPC分类号： H01L21/50

    CPC分类号： G01R1/0735 ,  Y10T29/49156

    摘要： In the highly accurate thin film probe sheet which is used for the contact to electrode pads disposed in high density with narrow pitches resulting from the increase in integration degree of semiconductor chips and for the inspection of semiconductor chips, a large spatial region in which a metal film selectively removable relative to terminal metal is formed in advance is formed in the peripheral region around minute contact terminals having sharp tips and disposed in high density with narrow pitches equivalent to those of the electrode pads. Thus, occurrence of damage in an inspection process is significantly reduced, and an inspection device simultaneously achieving the miniaturization and the durability can be provided.

    摘要翻译： 在用于与由半导体芯片的集成度增加和半导体芯片的检查而产生的窄间距高密度设置的电极焊盘接触的高精度薄膜探针片中，其中金属 在具有尖锐尖端的微小接触端子周围的周边区域中预先形成相对于端子金属可选择的膜，并以与电极焊盘相同的窄间距高密度地设置。 因此，检查过程中的损坏的发生显着减少，并且可以提供同时实现小型化和耐久性的检查装置。