公开(公告)号：US5017973A

公开(公告)日：1991-05-21

申请号：US287738

申请日：1988-12-21

申请人： Hiroshi Mizuta ,  Tomonori Tanoue ,  Chushirou Kusano ,  Susumu Takahashi

发明人： Hiroshi Mizuta ,  Tomonori Tanoue ,  Chushirou Kusano ,  Susumu Takahashi

IPC分类号： H01L29/15 ,  H01L29/201 ,  H01L29/205 ,  H01L29/68 ,  H01L29/88

CPC分类号： B82Y10/00 ,  H01L29/155 ,  H01L29/882

摘要： A resonant tunneling device includes a superlattice layer which includes an interlaminated structure of three semiconductor layers each having a narrow energy bandgap and serving as a quantum well layer and four semiconductor layers each having a wide energy bandgap and serving as a barrier layer and in which three quantum levels are formed in the quantum well layers. A resonant tunneling phenomenon produced between the quantum levels provides peak current values which are substantially equal to each other, peak voltages which can be set independently from each other, and peak-to-valley (P/V) ratios which are high, thereby realizing a resonant tunneling device which has an excellent performance as a three state logic element for a logic circuit. By increasing the number of quantum well layers and the number of barrier layers, a logic element of four or more states can be realized for a logic circuit.

公开(公告)号：US5229623A

公开(公告)日：1993-07-20

申请号：US746288

申请日：1991-08-13

申请人： Tomonori Tanoue ,  Hiroshi Mizuta ,  Susumu Takahashi

发明人： Tomonori Tanoue ,  Hiroshi Mizuta ,  Susumu Takahashi

IPC分类号： G02F3/02 ,  G06N3/063 ,  G06N3/067 ,  G11C11/56

CPC分类号： B82Y10/00 ,  G02F3/028 ,  G06N3/0635 ,  G06N3/0675 ,  G11C11/56 ,  G11C13/04 ,  G11C2211/5614

摘要： A semiconductor device is disclosed, which includes a multiple negative differential resistance element having negative differential resistance characteristics at at least two places in the current-voltage characteristics, and which is suitable for constructing a neural network having a high density integration and a high reliability.

摘要翻译： 公开了一种半导体器件，其包括在电流 - 电压特性中的至少两个位置具有负的差分电阻特性的多个负的差分电阻元件，并且适用于构建具有高密度集成和高可靠性的神经网络。

公开(公告)号：US06211531B1

公开(公告)日：2001-04-03

申请号：US09492171

申请日：2000-01-27

申请人： Kazuo Nakazato ,  Kiyoo Itoh ,  Hiroshi Mizuta ,  Toshikazu Shimada ,  Hideo Sunami ,  Tatsuya Teshima ,  Toshiyuki Mine ,  Ken Yamaguchi

发明人： Kazuo Nakazato ,  Kiyoo Itoh ,  Hiroshi Mizuta ,  Toshikazu Shimada ,  Hideo Sunami ,  Tatsuya Teshima ,  Toshiyuki Mine ,  Ken Yamaguchi

IPC分类号： H01L2906

CPC分类号： H01L27/10858 ,  B82Y10/00 ,  G11C11/16 ,  H01L21/28273 ,  H01L27/10808 ,  H01L27/1082 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/11 ,  H01L29/154 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/772 ,  H01L29/78609 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78687 ,  H01L29/7881 ,  H01L29/882

摘要： A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer structure 3 providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.

摘要翻译： 晶体管形式的可控导电器件包括源极和漏极区域5，其间延伸用于电荷载流子的导电路径P，用于控制沿导电路径的电荷载流子的栅极4和提供多个 导通路径中的隧道结结构，结果当晶体管处于其截止状态时，漏电流被多重隧道结构造阻塞。 描述了垂直和横向晶体管配置，以及使用晶体管的互补对和随机存取存储器单元。 描述了改进的栅极结构，其也适用于结合隧道势垒配置以在存储器节点上存储电荷的存储器件。

公开(公告)号：US07132713B2

公开(公告)日：2006-11-07

申请号：US10121596

申请日：2002-04-15

申请人： Kazuo Nakazato ,  Kiyoo Itoh ,  Hiroshi Mizuta ,  Toshikazu Shimada ,  Hideo Sunami ,  Tatsuya Teshima ,  Toshiyuki Mine ,  Ken Yamaguchi

发明人： Kazuo Nakazato ,  Kiyoo Itoh ,  Hiroshi Mizuta ,  Toshikazu Shimada ,  Hideo Sunami ,  Tatsuya Teshima ,  Toshiyuki Mine ,  Ken Yamaguchi

IPC分类号： H01L29/76 ,  H01L31/109

CPC分类号： H01L27/10858 ,  B82Y10/00 ,  G11C11/16 ,  H01L21/28273 ,  H01L27/10808 ,  H01L27/1082 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/11 ,  H01L29/154 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/772 ,  H01L29/78609 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78687 ,  H01L29/7881 ,  H01L29/882

摘要： A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer structure 3 providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.

摘要翻译： 晶体管形式的可控导电器件包括源极和漏极区域5，其间延伸用于电荷载流子的导电路径P，用于控制沿导电路径的电荷载流子的栅极4和提供多个 导通路径中的隧道结结构，结果当晶体管处于其截止状态时，漏电流被多重隧道结构造阻塞。 描述了垂直和横向晶体管配置，以及使用晶体管的互补对和随机存取存储器单元。 描述了改进的栅极结构，其也适用于结合隧道势垒配置以在存储器节点上存储电荷的存储器件。

公开(公告)号：US6060723A

公开(公告)日：2000-05-09

申请号：US95058

申请日：1998-06-10

申请人： Kazuo Nakazato ,  Kiyoo Itoh ,  Hiroshi Mizuta ,  Toshikazu Shimada ,  Hideo Sunami ,  Tatsuya Teshima ,  Toshiyuki Mine ,  Ken Yamaguchi

发明人： Kazuo Nakazato ,  Kiyoo Itoh ,  Hiroshi Mizuta ,  Toshikazu Shimada ,  Hideo Sunami ,  Tatsuya Teshima ,  Toshiyuki Mine ,  Ken Yamaguchi

IPC分类号： G11C11/16 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/108 ,  H01L27/11 ,  H01L29/15 ,  H01L29/423 ,  H01L29/772 ,  H01L29/786 ,  H01L29/788 ,  H01L29/88 ,  H01L29/06 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L27/10858 ,  B82Y10/00 ,  G11C11/16 ,  H01L21/28273 ,  H01L27/10808 ,  H01L27/1082 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/11 ,  H01L29/154 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/772 ,  H01L29/78609 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78687 ,  H01L29/7881 ,  H01L29/882

摘要： A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer structure 3 providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.

公开(公告)号：US06753568B1

公开(公告)日：2004-06-22

申请号：US09362200

申请日：1999-07-28

申请人： Kazuo Nakazato ,  Kiyoo Itoh ,  Hiroshi Mizuta ,  Toshihiko Sato ,  Toshikazu Shimada ,  Haroon Ahmed

发明人： Kazuo Nakazato ,  Kiyoo Itoh ,  Hiroshi Mizuta ,  Toshihiko Sato ,  Toshikazu Shimada ,  Haroon Ahmed

IPC分类号： H01L2976

CPC分类号： H01L21/28185 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/02 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/772 ,  H01L29/78642 ,  H01L29/7883 ,  H01L29/7888

摘要： A memory device includes a memory node (1) to which charge is written through a tunnel barrier configuration (2) from a control electrode (9). The stored charge effects the conductivity of a source/drain path (4) and data is read by monitoring the conductivity of the path. The charge barrier configuration comprises a multiple tunnel barrier configuration, which may comprise alternating layers (16) of polysilicon of 3 nm thickness and layers (15) of Si3N4 of 1 nm thickness, overlying polycrystalline layer of silicon (1) which forms the memory node. Alternative barrier configurations (2) are described, including a Schottky barrier configuration, and conductive nanometer scale conductive islands (30, 36, 44), which act as the memory node, distributed in an electrically insulating matrix.

摘要翻译： 存储器件包括从控制电极（9）通过隧道势垒配置（2）写入电荷的存储器节点（1）。 存储的电荷影响源/漏路径（4）的电导率，并且通过监测路径的电导率来读取数据。 电荷势垒配置包括多隧道势垒结构，其可以包括3nm厚度的多晶硅的交替层（16）和1nm厚度的Si 3 N 4层（15），覆盖形成存储器节点的硅的多晶层（1） 。 描述了包括肖特基势垒结构的替代屏障配置（2）和用作存储节点的导电纳米级导电岛（30,36,44），其分布在电绝缘矩阵中。

公开(公告)号：US06169308A

公开(公告)日：2001-01-02

申请号：US09166858

申请日：1998-10-06

申请人： Hideo Sunami ,  Kiyoo Itoh ,  Toshikazu Shimada ,  Kazuo Nakazato ,  Hiroshi Mizuta

发明人： Hideo Sunami ,  Kiyoo Itoh ,  Toshikazu Shimada ,  Kazuo Nakazato ,  Hiroshi Mizuta

IPC分类号： H01L2972

CPC分类号： B82Y10/00 ,  G11C16/02 ,  H01L27/108 ,  H01L27/1082 ,  H01L27/10858 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/11 ,  H01L29/154 ,  H01L29/42324 ,  H01L29/511 ,  H01L29/772 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78687 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/7888

摘要： A high speed/large capacity DRAM (Dynamic Random Access Memory) is generally refreshed each 0.1 sec because it loses information stored therein due to a leakage current. The DRAM also loses information stored therein upon cutoff of a power source. Meanwhile, a nonvolatile ROM (Read-only Memory) cannot be configured as a high speed/large capacity memory. A semiconductor memory device of the present invention realizes nonvolatile characteristic by shielding a drain functioning as a memory node from a leakage current by a tunnel insulator, and also realizes stable and high speed operation by adding a transistor for reading to a memory cell.

摘要翻译： 通常由于漏电流而丢失存储在其中的信息，所以每0.1秒钟通常刷新高速/大容量DRAM（动态随机存取存储器）。 在断电时，DRAM也会丢失存储在其中的信息。 同时，非易失性ROM（只读存储器）不能被配置为高速/大容量存储器。本发明的半导体存储器件通过屏蔽用作存储器节点的漏极与隧道的泄漏电流来实现非易失性特性 绝缘体，并且通过将用于读取的晶体管添加到存储单元来实现稳定和高速操作。

公开(公告)号：US20050051805A1

公开(公告)日：2005-03-10

申请号：US10887860

申请日：2004-07-12

申请人： Byong Kim ,  Kazuo Nakazato ,  Hiroshi Mizuta

发明人： Byong Kim ,  Kazuo Nakazato ,  Hiroshi Mizuta

IPC分类号： B82B1/00 ,  G11C13/02 ,  H01L21/337 ,  H01L21/338 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/06 ,  H01L29/74 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792 ,  H01L29/808 ,  H01L29/812 ,  H01L51/30 ,  H01L51/40

CPC分类号： H01L51/0048 ,  B82Y10/00 ,  G11C13/025 ,  G11C2213/18 ,  H01L51/002 ,  H01L51/0508 ,  H01L51/0545

摘要： A transistor device comprising source and drain regions (S, D), a nanotube structure (2, 3) providing a path for electrical charge carriers between the source and drain regions, and a gate region (4). The nanotube structure has its conduction band structure locally modified in the gate region, e.g. by doping, for controlling the passage of the charge carriers in the path. The device can be used as a flash memory or as a memory element in a DRAM.

摘要翻译： 一种晶体管器件，包括源极和漏极区域（S，D），提供源极和漏极区域之间的电荷载流子路径的纳米管结构（2,3）和栅极区域（4）。 纳米管结构具有在栅极区域局部修饰的导带结构。 通过掺杂，用于控制路径中的载流子的通过。 该装置可以用作DRAM中的闪存或存储元件。

公开(公告)号：US06833980B1

公开(公告)日：2004-12-21

申请号：US09504623

申请日：2000-02-15

申请人： Kazuhito Tsukagoshi ,  Bruce William Alphenaar ,  Hiroshi Mizuta

发明人： Kazuhito Tsukagoshi ,  Bruce William Alphenaar ,  Hiroshi Mizuta

IPC分类号： G11B533

CPC分类号： H01L43/08 ,  B82Y10/00 ,  B82Y25/00 ,  G01R33/09 ,  G11B5/332 ,  G11B5/37 ,  G11B5/3903 ,  G11B5/3909 ,  G11B2005/3996 ,  G11C13/025

摘要： A magnetoelectric device responsive to an applied magnetic field, e.g. for use as a reading head for data stored in magnetic storage media, comprises first and second ferromagnetic regions (3, 4) with a channel region (5) between them, the ferromagnetic regions being configured so that charge carriers with a particular spin polarization which can pass through the first region, pass through the second region as a function of the relative orientations of magnetization of the ferromagnetic regions produced by the applied magnetic field such that the device exhibits a conductivity as a function of the strength of the applied field. The channel region (5) includes a nanotube (6) which may be formed of carbon, configured to provide a quasi-one-dimensional channel to cause charge carriers which pass through the first ferromagnetic region to maintain their spin polarization as they pass towards the second ferromagnetic region. In an alternative embodiment a deposited carbon layer (14) is used in the channel region.

摘要翻译： 响应于所施加的磁场的磁电装置，例如， 用作用于存储在磁存储介质中的数据的读取头，包括在它们之间具有通道区域（5）的第一和第二铁磁区域（3,4），所述铁磁区域被配置为使得具有特定自旋极化的电荷载流子 可以通过第一区域，作为由施加的磁场产生的铁磁区域的磁化的相对取向的函数，穿过第二区域，使得该器件显示作为施加场强度的函数的导电率。 通道区域（5）包括可以由碳形成的纳米管（6），其构造成提供准一维通道，以引起通过第一铁磁区域的电荷载流子，以保持其自旋极化 第二铁磁区。 在替代实施例中，在沟道区域中使用沉积碳层（14）。

公开(公告)号：US06825527B2

公开(公告)日：2004-11-30

申请号：US10454527

申请日：2003-06-05

申请人： Hideo Sunami ,  Kiyoo Itoh ,  Toshikazu Shimada ,  Kazuo Nakazato ,  Hiroshi Mizuta

发明人： Hideo Sunami ,  Kiyoo Itoh ,  Toshikazu Shimada ,  Kazuo Nakazato ,  Hiroshi Mizuta

IPC分类号： H01L2972

CPC分类号： B82Y10/00 ,  G11C16/02 ,  H01L27/108 ,  H01L29/511 ,  H01L29/772 ,  H01L29/785 ,  H01L29/78642 ,  H01L29/7883 ,  H01L29/7888

摘要： A high speed/large capacity DRAM (Dynamic Random Access Memory) is generally refreshed each 0.1 sec because it loses information stored therein due to a leakage current. The DRAM also loses information stored therein upon cutoff of a power source. Meanwhile, a nonvolatile ROM (Read-only Memory) cannot be configured as a high speed/large capacity memory. A semiconductor memory device of the present invention realizes nonvolatile characteristic by shielding a drain functioning as a memory node from a leakage current by a tunnel insulator, and also realizes stable and high speed operation by adding a transistor for reading to a memory cell.

摘要翻译： 通常由于漏电流而丢失存储在其中的信息，所以每0.1秒钟通常刷新高速/大容量DRAM（动态随机存取存储器）。 在断电时，DRAM也会丢失存储在其中的信息。 同时，非易失性ROM（只读存储器）不能被配置为高速/大容量存储器。本发明的半导体存储器件通过屏蔽用作存储器节点的漏极与隧道的泄漏电流来实现非易失性特性 绝缘体，并且通过将用于读取的晶体管添加到存储单元来实现稳定和高速操作。